AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 76

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

13.2
13.3
13.4
76
Hardware Interrupt Vectoring
Priority Controller
Interrupt Handling
AT91FR40162S Preliminary
The hardware interrupt vectoring reduces the number of instructions to reach the interrupt han-
dler to only one. By storing the following instruction at address 0x00000018, the processor loads
the program counter with the interrupt handler address stored in the AIC_IVR register. Execution
is then vectored to the interrupt handler corresponding to the current interrupt.
The current interrupt is the interrupt with the highest priority when the Interrupt Vector Register
(AIC_IVR) is read. The value read in the AIC_IVR corresponds to the address stored in the
Source Vector Register (AIC_SVR) of the current interrupt. Each interrupt source has its corre-
sponding AIC_SVR. In order to take advantage of the hardware interrupt vectoring it is
necessary to store the address of each interrupt handler in the corresponding AIC_SVR, at sys-
tem initialization.
The NIRQ line is controlled by an 8-level priority encoder. Each source has a programmable pri-
ority level of 7 to 0. Level 7 is the highest priority and level 0 the lowest.
When the AIC receives more than one unmasked interrupt at a time, the interrupt with the high-
est priority is serviced first. If both interrupts have equal priority, the interrupt with the lowest
interrupt source number is serviced first (see
The current priority level is defined as the priority level of the current interrupt at the time the reg-
ister AIC_IVR is read (the interrupt which will be serviced).
In the case when a higher priority unmasked interrupt occurs while an interrupt already exists,
there are two possible outcomes depending on whether the AIC_IVR has been read.
When the end of interrupt command register (AIC_EOICR) is written the current interrupt level is
updated with the last stored interrupt level from the stack (if any). Hence at the end of a higher
priority interrupt, the AIC returns to the previous state corresponding to the preceding lower pri-
ority interrupt which had been interrupted.
The interrupt handler must read the AIC_IVR as soon as possible. This de-asserts the NIRQ
request to the processor and clears the interrupt in case it is programmed to be edge triggered.
This permits the AIC to assert the NIRQ line again when a higher priority unmasked interrupt
occurs.
At the end of the interrupt service routine, the end of interrupt command register (AIC_EOICR)
must be written. This allows pending interrupts to be serviced.
• If the NIRQ line has been asserted but the AIC_IVR has not been read, then the processor
• If the processor has already read the AIC_IVR then the NIRQ line is reasserted. When the
will read the new higher priority interrupt handler address in the AIC_IVR register and the
current interrupt level is updated.
processor has authorized nested interrupts to occur and reads the AIC_IVR again, it reads
the new, higher priority interrupt handler address. At the same time the current priority value
is pushed onto a first-in last-out stack and the current priority is updated to the higher priority.
ldr
PC,[PC,# - &F20]
Table 13-1 on page
75).
6174B–ATARM–07-Nov-05