AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 150

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

18.3.3
18.3.4
18.3.5
150
AT91FR40162S Preliminary
Clock Control
Timer Counter Operating Modes
Trigger
The clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped.
Figure 18-3. Clock Control
Each Timer Counter channel can independently operate in two different modes:
The Timer Counter Operating Mode is programmed with the WAVE bit in the TC Mode Register.
In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always
configured to be an output and TIOB is an output if it is not selected to be the external trigger.
A trigger resets the counter and starts the counter clock. Three types of triggers are common to
both modes, and a fourth external trigger is available to each mode.
The following triggers are common to both modes:
• The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS
• The clock can also be started or stopped: a trigger (software, synchro, external or compare)
• Capture Mode allows measurement on signals
• Waveform Mode allows wave generation
commands in the Control Register. In Capture Mode it can be disabled by an RB load event if
LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare
event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no
effect: only a CLKEN command in the Control Register can re-enable the clock. When the
clock is enabled, the CLKSTA bit is set in the Status Register.
always starts the clock. The clock can be stopped by an RB load event in Capture Mode
(LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in
TC_CMR). The start and the stop commands have effect only if the clock is enabled.
Selected
Counter
Clock
Clock
Q
R
S
Trigger
CLKSTA
Q
CLKEN
S
R
Event
Stop
CLKDIS
Disable
Event
6174B–ATARM–07-Nov-05