AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 92

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AT91FR40162S-CJ

Manufacturer Part Number
AT91FR40162S-CJ
Description
IC ARM MCU FLASH 1K 121BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91FR40162S-CJ

Core Processor
ARM7
Core Size
16/32-Bit
Speed
75MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
2MB (1M x 16)
Program Memory Type
FLASH
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
121-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-

Available stocks

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14.4
14.5
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Interrupts
User Interface
AT91FR40162S Preliminary
Each parallel I/O can be programmed to generate an interrupt when a level change occurs. This
is controlled by the PIO_IER (Interrupt Enable) and PIO_IDR (Interrupt Disable) registers which
enable/disable the I/O interrupt by setting/clearing the corresponding bit in the PIO_IMR. When
a change in level occurs, the corresponding bit in the PIO_ISR (Interrupt Status) is set whether
the pin is used as a PIO or a peripheral and whether it is defined as input or output. If the corre-
sponding interrupt in PIO_IMR (Interrupt Mask) is enabled, the PIO interrupt is asserted.
When PIO_ISR is read, the register is automatically cleared.
Each individual I/O is associated with a bit position in the Parallel I/O user interface registers.
Each of these registers are 32 bits wide. If a parallel I/O line is not defined, writing to the corre-
sponding bits has no effect. Undefined bits read zero.
6174B–ATARM–07-Nov-05

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