C8051F350 Silicon Laboratories Inc, C8051F350 Datasheet - Page 101
![IC 8051 MCU 8K FLASH 32LQFP](/photos/15/92/159269/tqfp-32_sml.jpg)
C8051F350
Manufacturer Part Number
C8051F350
Description
IC 8051 MCU 8K FLASH 32LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F35xr
Specifications of C8051F350
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x24b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
Data Bus Width
8 bit
Data Rom Size
128 B
On-chip Adc
10 bit
Number Of Timers
16 bit
Operating Supply Voltage
2.7 V to 3.6 V
Mounting Style
SMD/SMT
Height
1.4 mm
Length
7 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Width
7 mm
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Part Number:
C8051F350
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Silicon Laboratories Inc
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12.4. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bit 3:
Bit 2:
Bit 1:
Bit 0:
R/W
EA
Bit7
EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask set-
tings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
ESPI0: Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
ES0: Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
EX1: Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
EX0: Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 input.
ESPI0
R/W
Bit6
ET2
R/W
Bit5
Figure 12.1. IE: Interrupt Enable
ES0
R/W
Bit4
Rev. 0.4
ET1
R/W
Bit3
EX1
R/W
Bit2
C8051F350/1/2/3
ET0
R/W
Bit1
SFR Address:
EX0
R/W
Bit0
0xA8
00000000
Addressable
Reset Value
Bit
101