C8051F350 Silicon Laboratories Inc, C8051F350 Datasheet - Page 25

• Manufacturer Part Number: C8051F350
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F350

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x24b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Data Bus Width: 8 bit
• Data Rom Size: 128 B
• On-chip Adc: 10 bit
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.4 mm
• Length: 7 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Width: 7 mm
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

1.8.
C8051F350/1/2/3 devices include 17 I/O pins. Port pins are organized as two byte-wide ports and one 1-bit
port. The port pins behave like typical 8051 ports with a few enhancements. Each port pin can be config-
ured as a digital or analog I/O pin. Pins selected as digital I/O can be configured for push-pull or open-drain
operation. The “weak pull-ups” that are fixed on typical 8051 devices may be globally disabled to save
power.
The Digital Crossbar allows mapping of internal digital system resources to port I/O pins. On-chip
conter/timers, serial buses, hardware interrupts, and other digital signals can be configured to appear on
the port pins using the Crossbar control resgiters. This allows the user to select the exact mix of general-
purpose port I/O, digital, and analog resources needed for the application.
Highest
Lowest
Priority
Priority
Port Input/Output
SYSCLK
Outputs
SMBus
T0, T1
UART
P0
P1
P2
PCA
CP0
SPI
(P0.0-P0.7)
(P1.0-P1.7)
Figure 1.10. Port I/O Functional Block Diagram
2
2
4
2
4
2
8
8
(P2.0)
PnSKIP Registers
XBR0, XBR1,
Crossbar
Rev. 0.4
Decoder
Priority
Digital
8
8
PnMDIN Registers
PnMDOUT,
C8051F350/1/2/3
Cells
Cells
Cell
I/O
I/O
I/O
P0
P1
P2
P0.0
P0.7
P1.0
P1.7
P2.0
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