C8051F350 Silicon Laboratories Inc, C8051F350 Datasheet - Page 63

• Manufacturer Part Number: C8051F350
• Description: IC 8051 MCU 8K FLASH 32LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F35xr

Specifications of C8051F350

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x24b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Data Bus Width: 8 bit
• Data Rom Size: 128 B
• On-chip Adc: 10 bit
• Number Of Timers: 16 bit
• Operating Supply Voltage: 2.7 V to 3.6 V
• Mounting Style: SMD/SMT
• Height: 1.4 mm
• Length: 7 mm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Width: 7 mm
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No RoHS Version Available

Bit 7:
Bits 6-4: IDA0CM[2:0]: IDA0 Update Source Select bits.
Bit 3:
Bit 2:
Bits 1:0: IDA0OMD[1:0]: IDA0 Output Mode Select bits.
Bits 7-0: IDA0 Data Word Bits.
IDA0EN
R/W
R/W
Bit7
Bit7
IDA0EN: IDA0 Enable.
0: IDA0 Disabled.
1: IDA0 Enabled.
000: DAC output updates on Timer 0 overflow.
001: DAC output updates on Timer 1 overflow.
010: DAC output updates on Timer 2 overflow.
011: DAC output updates on Timer 3 overflow.
100: DAC output updates on rising edge of CNVSTR.
101: DAC output updates on falling edge of CNVSTR.
110: DAC output updates on any edge of CNVSTR.
111: DAC output updates on write to IDA0.
IDA0CSC: IDA0 Constant Supply Current.
0: Current draw on V
1: Current draw on V
Unused. Read = 0b, Write = Don’t Care.
00: 0.25 mA full-scale output current.
01: 0.5 mA full-scale output current.
10: 1.0 mA full-scale output current.
11: 2.0 mA full-scale output current.
Bits 7-0 hold the 8-bit IDA0 Data Word.
R/W
R/W
Bit6
Bit6
Figure 6.3. IDA0CN: IDA0 Control Register
Figure 6.4. IDA0: IDA0 Data Word Register
IDA0CM
R/W
R/W
Bit5
Bit5
DD
DD
is dependent on IDA0 Output Word.
is independent of IDA0 Output Word.
R/W
R/W
Bit4
Bit4
IDA0CSC
Rev. 0.4
R/W
R/W
Bit3
Bit3
R/W
Bit2
Bit2
R
-
C8051F350/1/2/3
R/W
R/W
Bit1
Bit1
IDA0OMD
SFR Address:
SFR Address:
R/W
R/W
Bit0
Bit0
0x96
0xB9
00000000
Reset Value
Reset Value
01110000
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