HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 10

• Manufacturer Part Number: HD64F2378RVFQ33
• Description: IC H8S MCU FLASH 512K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2378RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Item
Section 8 EXDMA
Controller (EXDMAC)
8.3.5 EXDMA
Address Control
Register (EDACR)
8.4.2 Address Modes
Single Address Mode:
Rev.7.00 Mar. 18, 2009 page viii of lxvi
REJ09B0109-0700
Page
359
370
372
376
Revision (See Manual for Details)
Description amended
… The EXDMAC can carry out high-speed data transfer, in
place of the CPU, to and from external devices and external
memory with a DACK (DMA transfer notification) facility.
Table amended
Bit
15
14
Table amended
Bit
7
6
Description amended
… In the example of transfer between external memory and an
external device with DACK shown in figure 8.3, data is output to
the data bus by the external device and written to external
memory in the same bus cycle.
The transfer direction, that is whether the external device with
DACK is the transfer source or transfer destination, can be
specified with the SDIR bit in EDMDR. Transfer is performed
from the external memory (EDSAR) to the external device with
DACK when SDIR = 0, and from the external device with DACK
to the external memory (EDDAR) when SDIR = 1.
Bit Name
SAT1
SAT0
Bit Name
DAT1
DAT0
Initial Value
0
0
Initial Value
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Source Address Update Mode
These bits specify incrementing/decrementing of
the transfer source address (EDSAR). When an
external device with DACK is designated as the
transfer source in single address mode, the
specification by these bits is ignored.
0×: Fixed
10: Incremented (+1 in byte transfer, +2 in word
11: Decremented (–1 in byte transfer, –2 in word
Description
Destination Address Update Mode
These bits specify incrementing/decrementing of
the transfer destination address (EDDAR). When
an external device with DACK is designated as the
transfer destination in single address mode, the
specification by these bits is ignored.
0×: Fixed
10: Incremented (+1 in byte transfer, +2 in word
11: Decremented (–1 in byte transfer, –2 in word
transfer)
transfer)
transfer)
transfer)