HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 308
![IC H8S MCU FLASH 512K 144-LQFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
HD64F2378RVFQ33
Manufacturer Part Number
HD64F2378RVFQ33
Description
IC H8S MCU FLASH 512K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of HD64F2378RVFQ33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
97
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 6x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Section 6 Bus Controller (BSC)
6.7.14
Mode Register Setting of Synchronous DRAM
To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to
RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After
that, access the continuous synchronous DRAM space in bytes. When the value to be set in the
synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register
by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus
configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of
address H'400000 + 2X for 16-bit bus configuration synchronous DRAM.
The value of the address signal is fetched at the issuance time of the MRS command as the setting
value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the
synchronous DRAM is not supported by this LSI. For setting the mode register of the
synchronous DRAM, set the burst read/single write with the burst length of 1. Figure 6.59 shows
the setting timing of the mode in the synchronous DRAM.
T
T
T
T
p
r
c1
c2
φ
SDRAMφ
Address bus
Mode setting value
Mode setting value
Precharge-sel
RAS
CAS
WE
CKE
High
PALL
NOP
MRS
NOP
Figure 6.59 Synchronous DRAM Mode Setting Timing
Rev.7.00 Mar. 18, 2009 page 240 of 1136
REJ09B0109-0700
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