HD64F2378RVFQ33 Renesas Electronics America, HD64F2378RVFQ33 Datasheet - Page 453

• Manufacturer Part Number: HD64F2378RVFQ33
• Description: IC H8S MCU FLASH 512K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of HD64F2378RVFQ33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 97
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 6x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

mode, the block size must be a power of two, or alternatively, the address register value must be
set so that the end of a block coincides with the end of the repeat area range.
If repeat area overflow occurs while a block is being transferred in block transfer mode, the repeat
interrupt request is held pending until the end of the block, and transfer overrun will occur. Figure
8.10 shows an example in which block transfer mode is used together with the repeat area
function.
8.4.7
EXDMAC register values are updated as DMA transfer processing is performed. The updated
values depend on various settings and the transfer status. The following registers and bits are
updated: EDSAR, EDDAR, EDTCR, and bits EDA, BEF, and IRF in EDMDR,
EXDMA Source Address Register (EDSAR): When the EDSAR address is accessed as the
transfer source, after the EDSAR value is output, EDSAR is updated with the address to be
When lower 3 bits (8-byte area) of EDSAR are designated as repeat area (SARA4 to SARA0 = 3),
and block size of 5 (EDTCR[23–16] = 5) is set in block transfer mode
External memory
Figure 8.10 Example of Repeat Area Function Operation in Block Transfer Mode
H'23FFFE
H'23FFFF
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
H'240008
H'240009
Registers during DMA Transfer Operation
:
:
EDSAR values
H'240000
H'240001
H'240002
H'240003
H'240004
H'240005
H'240006
H'240007
Range of
First block
H'240000
H'240001
H'240002
H'240003
H'240004
transfer
Rev.7.00 Mar. 18, 2009 page 385 of 1136
Section 8 EXDMA Controller (EXDMAC)
Second block
H'240000
H'240001
H'240005
H'240006
H'240007
transfer
REJ09B0109-0700
Block transfer
in progress
Interrupt
requested