SAF-C161U-LF V1.3 Infineon Technologies, SAF-C161U-LF V1.3 Datasheet - Page 54

• Manufacturer Part Number: SAF-C161U-LF V1.3
• Description: IC MCU ISDN 16BIT TTL TQFP-100
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAF-C161U-LF V1.3

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 36MHz
• Connectivity: EBI/EMI, SPI, UART/USART, USB
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Type: ROMless
• Ram Size: 3K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Other names: SAFC161ULFV1.3X; SAFC161ULFV13XP; SP000007502

Data Sheet
5
Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the
arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and
to store the previously calculated results. As the CPU is the main engine of the C161U
controller, it is also affected by certain actions of the peripheral subsystem.
Since a four stage pipeline is implemented in the C161U, up to four instructions can be
processed in parallel. Most instructions of the C161U are executed in one machine cycle
(2 CPU clock cycles) due to this parallelism. This chapter describes how the pipeline
works for sequential and branch instructions in general, and which hardware provisions
have been made to speed the execution of jump instructions in particular. The general
instruction timing is described including standard and exceptional timing.
While internal memory accesses are normally performed by the CPU itself, external
peripheral or memory accesses are performed by a particular on-chip External Bus
Controller (EBC), which is automatically invoked by the CPU whenever a code or data
address refers to the external address space. If possible, the CPU continues operating
while an external memory access is in progress. If external data are required but are not
yet available, or if a new external memory access is requested by the CPU, before a
previous access has been completed, the CPU will be held by the EBC until the request
can be satisfied. The EBC is described in a dedicated chapter.
Figure 12
ROM
Central Processor Unit
CPU Block Diagram
32
Data Page Ptr.
Exec. Unit
Instr. Reg.
SYSCON
Instr. Ptr.
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
STKUN
STKOV
PSW
SP
Pipeline
4-Stage
Barrel - Shifter
Bit-Mask Gen
Code Seg. Ptr.
Mul/Div-HW
Context Ptr.
ADDRSEL 1
ADDRSEL 2
ADDRSEL 3
ADDRSEL 4
ALU
MDH
CPU
MDL
54
(16-bit)
Registers
Purpose
General
R15
R0
Central Processor Unit
16
16
Internal
2001-04-19
RAM
R15
R0
MCB02147
C161U