MAX3798ETJ+ Maxim Integrated Products, MAX3798ETJ+ Datasheet - Page 13

• Manufacturer Part Number: MAX3798ETJ+
• Description: IC LIMITING AMP/VCSEL DVR 32TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3798ETJ+

• Amplifier Type: Limiting
• Number Of Circuits: 1
• Output Type: Differential
• Current - Supply: 97mA
• Voltage - Supply, Single/dual (±): 2.85 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Operating Temperature Range: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• -3db Bandwidth: -
• Slew Rate: -
• Gain Bandwidth Product: -
• Current - Input Bias: -
• Voltage - Input Offset: -
• Lead Free Status / Rohs Status: Details

(V
default values unless otherwise noted, and the 3-wire interface is static during measurements. For testing, the MODE_SEL bit was
used and the MSEL pin was left open.)
Power SFP+ Limiting Amplifier and VCSEL Driver
3, 6, 27, 30
12, 15, 18,
CC
PIN
= 3.3V, T
10
11
21
13
1
2
4
5
7
8
9
1.0625Gbps to 10.32Gbps, Integrated, Low-
A
= +25°C, unless otherwise specified. Figure 1 shows the typical setup used for measurements. Registers are set to
DISABLE
ROUT+
NAME
ROUT-
MSEL
CSEL
V
V
TIN+
V
LOS
SCL
SDA
CCR
CCD
CCT
______________________________________________________________________________________
Typical Operating Characteristics—VCSEL Driver (continued)
10
9
8
7
6
5
4
3
2
-7
PATTERN = PRBS, DATA RATE = 10.32Gbps
-5
Loss-of-Signal Output, Open Drain. The default polarity of LOS is high when the level of the input
signal is below the preset threshold set by the SET_LOS DAC. Polarity of the LOS function can be
inverted by setting LOS_POL = 0. The LOS circuitry can be disabled by setting the bit LOS_EN = 0.
Mode-Select Input, TTL/CMOS. Set the MSEL pin or MODE_SEL bit (set by the 3-wire digital interface)
to logic-high for high-bandwidth mode. Setting MSEL and MODE_SEL logic-low for high-gain mode.
The MSEL pin is internally pulled down by a 75k
Power Supply. Provides supply voltage to the receiver block.
Noninverted Receive Data Output, CML. Back-terminated for 50
Inverted Receive Data Output, CML. Back-terminated for 50
Power Supply. Provides supply voltage for the digital block.
Transmitter Disable Input, TTL/CMOS. Set to logic-low for normal operation. Logic-high or open
disables both the modulation and bias current. Internally pulled up by an 8k resistor to V
Serial Clock Input, TTL/CMOS. This pin has a 75k
Serial Data Bidirectional Input, TTL/CMOS. Open-drain output. This pin has a 75k
but it requires an external 4.7k pullup resistor to meet the 3-wire digital timing specification. (Data
line collision protection is implemented.)
Chip-Select Input, TTL/CMOS. Setting CSEL to logic-high starts a cycle. Setting CSEL to logic-low
ends the cycle and resets the control state machine. Internally pulled down by a 75k resistor to
ground.
Power Supply. Provides supply voltage to the transmitter block.
Noninverted Transmit Data Input, CML
vs. PULSE-WIDTH SETTING
DETERMINISTIC JITTER
-3
SET_PWCTRL[3:0]
UP
EYE CROSSING
-1
DOWN
1
3
5
7
FUNCTION
800
700
600
500
400
300
200
100
0
-40
resistor to ground.
internal pulldown.
-25 -10
BIAS MONITOR CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
5
I
load.
BIAS
I
I
BIAS
BIAS
20
= 12mA
= 8mA
= 2mA
load.
35
50
Pin Description
65
80
95
internal pullup,
CCT
.
13