MAX3798ETJ+ Maxim Integrated Products, MAX3798ETJ+ Datasheet - Page 7

• Manufacturer Part Number: MAX3798ETJ+
• Description: IC LIMITING AMP/VCSEL DVR 32TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3798ETJ+

• Amplifier Type: Limiting
• Number Of Circuits: 1
• Output Type: Differential
• Current - Supply: 97mA
• Voltage - Supply, Single/dual (±): 2.85 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Operating Temperature Range: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• -3db Bandwidth: -
• Slew Rate: -
• Gain Bandwidth Product: -
• Current - Input Bias: -
• Voltage - Input Offset: -
• Lead Free Status / Rohs Status: Details

ELECTRICAL CHARACTERISTICS (continued)
(V
put load is AC-coupled to differential 100Ω (see Figure 1), typical values are at +25°C, V
otherwise specified. Registers are set to default values unless otherwise noted, and the 3-wire interface is static during measure-
ments. For testing, the MODE_SEL bit was used and the MSEL pin was left open.)
Note 1: Supply current is measured with unterminated receiver CML output or with AC-coupled Rx output termination. The Tx out-
Note 2: Guaranteed by design and characterization, T
Note 3: The data input transition time is controlled by a 4th-order Bessel filter with -3dB frequency = 0.75 x data rate. The determin-
Note 4: Test pattern is 00001111 at 4.25Gbps for MODE_SEL = 0. Test pattern is 00001111 at 8.5Gbps for MODE_SEL = 1.
Power SFP+ Limiting Amplifier and VCSEL Driver
DISABLE Input Low Voltage
DISABLE Input Impedance
LOS, FAULT Output High Voltage
LOS, FAULT Output Low Voltage
3-WIRE DIGITAL I/O SPECIFICATIONS (SDA, CSEL, SCL)
Input High Voltage
Input Low Voltage
Input Hysteresis
Input Leakage Current
Output High Voltage
Output Low Voltage
3-WIRE DIGITAL INTERFACE TIMING CHARACTERISTICS (see Figure 4)
SCL Clock Frequency
SCL Pulse-Width High
SCL Pulse-Width Low
SDA Setup Time
SDA Hold Time
SCL Rise to SDA Propagation
Time
CSEL Pulse-Width Low
CSEL Leading Time Before the
First SCL Edge
CSEL Trailing Time After the
Last SCL Edge
SDA, SCL External Load
CC
= 2.85V to 3.63V, T
put and the bias current output must be connected to a separate supply in order to remove the modulation/bias current
portion from the supply current. BIAS must be connected to 2.0V. TOUT+/- must be connected through 50Ω load resistors
to a separate supply voltage.
istic jitter caused by this filter is not included in the DJ generation specifications.
PARAMETER
1.0625Gbps to 10.32Gbps, Integrated, Low-
_______________________________________________________________________________________
A
= -40°C to +85°C, CML receiver output load is AC-coupled to differential 100Ω, C
SYMBOL
R
V
I
IL
t
V
V
f
V
V
HYST
CSW
PULL
V
t
t
t
V
V
SCL
t
C
CH
DS
DH
t
CL
t
t
OH
, I
OH
OL
OL
D
IH
L
T
IL
IL
B
IH
Internal pullup resistor
R
R
R
R
V
(75k
External pullup of 4.7k
External pullup of 4.7k
Total bus capacitance on one line with
4.7k
IN
LOS
FAULT
LOS
FAULT
= 0V or V
A
= 4.7k
= 4.7k
typical)
pullup to V
= -40°C to +95°C.
= 4.7k
= 4.7k
CC
- 10k
- 10k
CONDITIONS
; internal pullup or pulldown
- 10k to V
- 10k to V
CC
to V
to V
to V
to V
CC
CC
CC
CC
,
,
CC
CC
CC
= 3.3V, I
V
V
MIN
500
5.5
0.5
2.0
0.5
0.5
0.5
CC
CC
0
0
BIAS
-
-
= 6mA, I
0.082
TYP
400
100
100
500
500
AZ
8
5
= 1nF, transmitter out-
MOD
MAX
1000
10.5
V
V
150
0.8
0.4
0.8
0.4
20
CC
CC
= 6mA, unless
UNITS
kHz
k
μA
μs
μs
ns
ns
ns
ns
ns
ns
pF
V
V
V
V
V
V
V
V
7