MAX3798ETJ+ Maxim Integrated Products, MAX3798ETJ+ Datasheet - Page 20

• Manufacturer Part Number: MAX3798ETJ+
• Description: IC LIMITING AMP/VCSEL DVR 32TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3798ETJ+

• Amplifier Type: Limiting
• Number Of Circuits: 1
• Output Type: Differential
• Current - Supply: 97mA
• Voltage - Supply, Single/dual (±): 2.85 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFN Exposed Pad
• Operating Temperature Range: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output / Channel: -
• -3db Bandwidth: -
• Slew Rate: -
• Gain Bandwidth Product: -
• Current - Input Bias: -
• Voltage - Input Offset: -
• Lead Free Status / Rohs Status: Details

1.0625Gbps to 10.32Gbps, Integrated, Low-
Power SFP+ Limiting Amplifier and VCSEL Driver
Table 3. Circuit Response to Single-Point Faults (continued)
The MAX3798 implements a proprietary 3-wire digital
interface. An external controller generates the clock. The
3-wire interface consists of an SDA bidirectional data
line, an SCL clock signal input, and a CSEL chip-select
input (active high). The external master initiates a data
transfer by asserting the CSEL pin. The master starts to
generate a clock signal after the CSEL pin has been set
to 1. All data transfers are most significant bit (MSB) first.
Each operation consists of 16-bit transfers (15-bit
address/data, 1-bit RWN). The bus master generates
16 clock cycles to SCL. All operations transfer 8 bits to
the MAX3798. The RWN bit determines if the cycle is
read or write. See Table 4.
The MAX3798 contains 17 registers available for pro-
gramming. Table 5 shows the registers and addresses.
The master generates 16 clock cycles at SCL in total.
The master outputs a total of 16 bits (MSB first) to the
SDA line at the falling edge of the clock. The master
closes the transmission by setting CSEL to 0. Figure 4
shows the interface timing.
Table 4. Digital Communication Word Structure
Note 1: Normal—Does not affect laser power.
Note 2: Supply-shorted current is assumed to be primarily on the circuit board (outside this device) and the main supply is
Note 3: Normal in functionality, but performance could be affected.
Warning: Shorted to V
20
15
PIN
31
32
______________________________________________________________________________________
collapsed by the short.
14
NAME
(V
CAZ2
CAZ1
EER
)
3-Wire Digital Communication
13
Register Address
CC
Normal (Note 1)
Disabled—Fault (external supply
shorted) (Note 2)
or shorted to ground on some pins can violate the Absolute Maximum Ratings .
12
SHORT TO V
11
Write Mode (RWN = 0)
Register Addresses
10
CC
Protocol
9
RWN
Normal (Note 1)
Normal (Note 3)—Redundant path
8
BIT
The master generates 16 clock cycles at SCL in total.
The master outputs a total of 8 bits (MSB first) to the
SDA line at the falling edge of the clock. The SDA line is
released after the RWN bit has been transmitted. The
slave outputs 8 bits of data (MSB first) at the rising edge
of the clock. The master closes the transmission by set-
ting CSEL to 0. Figure 4 shows the interface timing.
Normal mode allows read-only instruction for all regis-
ters except MODINC and BIASINC. The MODINC and
BIASINC registers can be updated during normal
mode. Doing so speeds up the laser control update
through the 3-wire interface by a factor of two. The nor-
mal mode is the default mode.
Setup mode allows the master to write unrestricted data
into any register except the status (TXSTAT1, TXSTAT2,
and RXSTAT) registers. To enter the setup mode, the
MODECTRL register (address = H0x0E) must be set to
H0x12. After the MODECTRL register has been set to
H0x12, the next operation is unrestricted. The setup
mode is automatically exited after the next operation is
finished. This sequence must be repeated if further
unrestricted settings are necessary.
SHORT TO GND
7
6
Data that is written or read.
5
4
Normal (Note 1)
Normal (Note 3)—Redundant path
3
Read Mode (RWN = 1)
OPEN
2
Mode Control
1
0