MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 143

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.3.2.3
The Flash module is in a low-power state if not being accessed. No recovery time is required after exit
from any low-power mode.
The MCF5280 does not have a Flash module.
7.3.2.4
The SCM’s core Watchdog timer can bring the device out of all low-power modes except stop mode. In
stop mode, all clocks stop, and the core Watchdog does not operate.
When enabled, the core Watchdog can bring the device out of low-power mode in one of two ways. If the
core Watchdog reset/interrupt select (CSRI) bit is set, then a core Watchdog timeout will cause a reset of
the device. If the CSRI bit is cleared, then a core Watchdog interrupt may be enabled and upon watchdog
timeout, can bring the device out of low-power mode. This system setup must meet the conditions
specified in
low-power mode.
7.3.2.5
SDRAMC operation is unaffected by either the wait or doze modes; however, the SDRAMC is disabled
by stop mode. Since all clocks to the SDRAMC are disabled by stop mode, the SDRAMC will not generate
refresh cycles.
To prevent loss of data the SDRAM should be placed in self-refresh mode by setting DCR[IS] before
entering stop mode. The SDRAM self-refresh mode allows the SDRAM to enter a low-power state where
internal refresh operations are used to maintain the integrity of the data stored in the SDRAM.
When stop mode is exited clearing the DCR[IS] bit will cause the SDRAM to exit the self-refresh mode
and allow bus cycles to the SDRAM to resume.
7.3.2.6
In wait and doze modes, the chip select module continues operation but does not generate interrupts;
therefore it cannot bring a device out of a low-power mode. This module is stopped in stop mode.
7.3.2.7
In wait and doze modes, the DMA controller is capable of bringing the device out of a low-power mode
by generating an interrupt either upon completion of a transfer or upon an error condition. The completion
of transfer interrupt is generated when DMA interrupts are enabled by the setting of the DCR[INT] bit,
and an interrupt is generated when the DSR[DONE] bit is set. The interrupt upon error condition is
generated when the DCR[INT] bit is set, and an interrupt is generated when either the CE, BES or BED
bit in the DSR becomes set.
The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode.
Freescale Semiconductor
Section 7.3.1, “Low-Power
Flash
System Control Module (SCM)
SDRAM Controller (SDRAMC)
Chip Select Module
DMA Controller (DMAC0–DMA3)
The SDRAM is inaccessible while in the self-refresh mode. Therefore, if
stop mode is used the vector table and any interrupt handlers that could
wake the processor should not be stored in or attempt to access SDRAM.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Modes” for the core Watchdog interrupt to bring the part out of
NOTE
Power Management
7-7