MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 386

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

General Purpose Timer Modules (GPTA and GPTB)
20.6.3
Setting an I/O select bit, IOSn, configures channel n as an output compare channel. The output compare
function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the
GPT counter reaches the value in the channel registers of an output compare channel, the timer can set,
clear, or toggle the channel pin. An output compare on channel n sets the CnF flag. The CnI bit enables the
CnF flag to generate interrupt requests.
The output mode and level bits, OMn and OLn, select, set, clear, or toggle on output compare. Clearing
both OMn and OLn disconnects the pin from the output logic.
Setting a force output compare bit, FOCn, causes an output compare on channel n. A forced output
compare does not set the channel flag.
A successful output compare on channel 3 overrides output compares on all other output compare
channels. A channel 3 output compare can cause bits in the output compare 3 data register to transfer to
the GPT port data register, depending on the output compare 3 mask register. The output compare 3 mask
register masks the bits in the output compare 3 data register. The GPT counter reset enable bit, TCRE,
enables channel 3 output compares to reset the GPT counter. A channel 3 output compare can reset the
GPT counter even if the OC3/PAI pin is being used as the pulse accumulator input.
An output compare overrides the data direction bit of the output compare pin but does not change the state
of the data direction bit.
Writing to the PORTTn bit of an output compare pin does not affect the pin state. The value written is
stored in an internal latch. When the pin becomes available for general-purpose output, the last value
written to the bit appears at the pin.
20.6.4
The pulse accumulator (PA) is a 16-bit counter that can operate in two modes:
The PA mode bit, PAMOD, selects the mode of operation.
The minimum pulse width for the PAI input is greater than two module clocks.
20.6.5
Clearing the PAMOD bit configures the PA for event counter operation. An active edge on the PAI pin
increments the PA. The PA edge bit, PEDGE, selects falling edges or rising edges to increment the PA.
An active edge on the PAI pin sets the PA input flag, PAIF. The PA input interrupt enable bit, PAI, enables
the PAIF flag to generate interrupt requests.
The PA counter register, GPTPACNT, reflects the number of active input edges on the PAI pin since the
last reset.
20-18
1. Event counter mode: counts edges of selected polarity on the pulse accumulator input pin, PAI
2. Gated time accumulation mode: counts pulses from a divide-by-64 clock
Output Compare
Pulse Accumulator
Event Counter Mode
The PAI input and GPT channel 3 use the same pin. To use the PAI input,
disconnect it from the output logic by clearing the channel 3 output mode
and output level bits, OM3 and OL3. Also clear the channel 3 output
compare 3 mask bit, OC3M3.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
NOTE
Freescale Semiconductor