MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 553

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

for queue 1 and a trigger event occurs for queue 1 with BQ2 set to 0. Queue 1 execution starts momentarily,
but is terminated after CCW0 is read. No conversions occur.
The BQ2[6:0] pointer may be changed dynamically to alternate between queue 2 scan sequences. A
change in BQ2 after queue 2 has begun or when queue 2 has a trigger pending does not affect queue 2 until
it is started again. For example, two scan sequences could be defined as follows: The first sequence starts
at CCW10, with a pause after CCW11 and an end of queue (EOQ) programmed in CCW15; the second
sequence starts at CCW16, with a pause after CCW17 and an EOQ programmed in CCW39.
With BQ2[6:0] set to CCW10 and the continuous-scan mode selected, queue execution begins. When the
pause is encountered in CCW11, an interrupt service routine can retarget BQ2[6:0] to CCW16. When the
end-of-queue is recognized in CCW15, an internal retrigger event is generated and execution restarts at
CCW16. When the pause software interrupt occurs again, BQ2 can be changed back to CCW10. After the
end-of-queue is recognized in CCW39, an internal retrigger event is created and execution now restarts at
CCW10.
If BQ2[6:0] is changed while queue 1 is active, the effect of BQ2[6:0] as an end-of-queue indication for
queue 1 is immediate. However, beware of the risk of losing the end-of-queue 1 when changing BQ2[6:0].
Using EOQ (channel 63) to end queue 1 is recommended.
Each time a CCW is read for queue 1, the CCW location is compared with the current value of the
BQ2[6:0] pointer to detect a possible end-of-queue condition. For example, if BQ2[6:0] is changed to
CCW3 while queue 1 is converting CCW2, queue 1 is terminated after the conversion is completed.
However, if BQ2[6:0] is changed to CCW1 while queue 1 is converting CCW2, the QADC would not
recognize a BQ2[6:0] end-of-queue condition until queue 1 execution reached CCW1 again, presumably
on the next pass through the queue.
Stop mode resets this register (0x007f)
Freescale Semiconductor
Address
Reset
Reset
R/W:
Field
R/W:
Field RESUME
If BQ2[6:0] was assigned to the CCW that queue 1 is currently working on,
then that conversion is completed before the change to BQ2[6:0] takes
effect.
CIE2
15
7
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
PIE2
BQ26
Figure 28-10. QADC Control Register 2 (QACR2)
14
6
SSE2
BQ25
13
5
IPSBAR + 0x19_000e, 0x19_000f
MQ212
NOTE
BQ24
12
4
0000_0000
0111_1111
R/W
R/W
MQ211
BQ23
11
3
MQ210
Queued Analog-to-Digital Converter (QADC)
BQ22
10
2
MQ29
BQ21
9
1
MQ28
BQ20
8
0
28-15