MCF5282CVM80 Freescale Semiconductor, MCF5282CVM80 Datasheet - Page 531

• Manufacturer Part Number: MCF5282CVM80
• Description: IC MPU 512K 80MHZ 256-MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVM80

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Controller Family/series: ColdFire
• Ram Memory Size: 64KB
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of Pwm Channels: 8
• Digital Ic Case Style: MAPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

27.4.3
If the external RCON pin is asserted during reset, then the states of these data pins during reset determine
the chip mode of operation, boot device, clock mode, and certain module configurations after reset.
27.5
This subsection provides a description of the memory map and registers.
27.5.1
The CCM programming model consists of these registers:
Some control register bits are implemented as write-once bits. These bits are always readable, but once the
bit has been written, additional writes have no effect, except during debug and test operations.
Some write-once bits can be read and written while in debug mode. When debug mode is exited, the chip
configuration module resumes operation based on the current register values. If a write to a write-once
register bit occurs while in debug mode, the register bit remains writable on exit from debug or test mode.
Table 27-2
27.5.2
1
2
3
Freescale Semiconductor
IPSBAR Offset
S = CPU supervisor mode access only. User mode accesses to supervisor only addresses have no effect and result in a cycle
termination transfer error.
See
this register.
Writing to reserved addresses with values other than 0 could put the device in a test mode; reading returns 0s.
0x0011_0004
0x0011_0008
0x0011_0010
0x0011_000c
•
•
•
Chapter 7, “Power
The chip configuration register (CCR) controls the main chip configuration.
The reset configuration register (RCON) indicates the default chip configuration.
The chip identification register (CIR) contains a unique part number.
Memory Map and Registers
D[26:24, 21, 19:16] (Reset Configuration Override)
Programming Model
shows the accessibility of write-once bits.
Memory Map
All configurations
Debug operation (all modes)
Master mode
Single-chip mode
Reset Configuration Register (RCON)
Chip Configuration Register (CCR)
Management,” for a description of the LPCR. It is shown here only to warn against accidental writes to
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 27-2. Write-Once Bits Read/Write Accessibility
Table 27-3. Chip Configuration Module Memory Map
Configuration
Bits 31–16
Unimplemented
Reserved
3
Low-Power Control Register (LPCR)
Read-always
Write-always
Write-once
Write-once
Chip Identification Register (CIR)
4
Read/Write Access
Bits 15–0
Chip Configuration Module (CCM)
2
Access
—
S
S
S
27-3
1