ATA5773-PXQW Atmel, ATA5773-PXQW Datasheet - Page 127
ATA5773-PXQW
Manufacturer Part Number
ATA5773-PXQW
Description
XMITTR UHF ASK/FSK 310MHZ 24VQFN
Manufacturer
Atmel
Datasheet
1.ATA5773-DK1.pdf
(219 pages)
Specifications of ATA5773-PXQW
Frequency
310MHz ~ 350MHz
Modulation Or Protocol
UHF
Power - Output
8dBm
Voltage - Supply
2 V ~ 4 V
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA5x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA5773-PXQW
Manufacturer:
ATMEL
Quantity:
3 500
Part Number:
ATA5773-PXQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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9137E–RKE–12/10
Figure 4-54. Three-wire Mode, Timing Diagram
The Three-wire mode timing is shown in
reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. The
USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0),
DI is sampled at positive edges, and DO is changed (Data Register is shifted by one) at nega-
tive edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e.,
samples data at negative and changes the output at positive edges. The USI clock modes cor-
responds to the SPI data mode 0 and 1.
Referring to the timing diagram
1. The Slave device and Master device sets up its data output and, depending on the pro-
2. The Master generates a clock pulse by software toggling the USCK line twice (C and
3. Step 2 is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that
tocol used, enables its output driver (mark A and B). The output is set up by writing the
data to be transmitted to the Serial Data Register. Enabling of the output is done by
setting the corresponding bit in the port Data Direction Register. Note that point A and
B does not have any specific order, but both must be at least one half USCK cycle
before point C where the data is sampled. This must be done to ensure that the data
setup requirement is satisfied. The 4-bit counter is reset to zero.
D). The bit value on the slave and master’s data input (DI) pin is sampled by the USI on
the first edge (C), and the data output is changed on the opposite edge (D). The 4-bit
counter will count both edges.
the transfer is completed. The data bytes transferred must now be processed before a
new transfer can be initiated. The overflow interrupt will wake up the processor if it is
set to Idle mode. Depending of the protocol used the slave device can now set its out-
put to high impedance.
CYCLE
USCK
USCK
DO
DI
( Reference )
A
B
MSB
MSB
C
1
D
2
6
6
(Figure
3
5
5
4-54), a bus transfer involves the following steps:
Figure
4
4
4
4-54. At the top of the figure is a USCK cycle
Atmel ATA5771/73/74
5
3
3
6
2
2
7
1
1
LSB
LSB
8
E
127
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