XRT75R03IVTR-F Exar Corporation, XRT75R03IVTR-F Datasheet - Page 61

• Manufacturer Part Number: XRT75R03IVTR-F
• Description: IC LIU E3/DS3/STS-1 3CH 128LQFP
• Manufacturer: Exar Corporation

Specifications of XRT75R03IVTR-F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

xr
xr
xr
xr
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
THE GLOBAL/CHIP-LEVEL REGISTERS
The register set, within the XRT75R03 consists of five "Global" or "Chip-Level" Registers and 21 per-Channel
Registers. This section will present detailed information on the Global Registers.
REGISTER DESCRIPTION - GLOBAL REGISTERS
N
UMBER
Reserved
B
0x01 - 0x1F
0x22 - 0x3D
7
6
IT
B
A
R/O
IT
DDRESS
0
0x3E
0x00
0x20
0x21
0x3F
7
RxON Ch 2
Reserved
T
ABLE
N
AME
RxONCh 2
B
R/W
Bank of Per-Channel Registers
18: APS/R
IT
0
6
T
C
Reserved Registers
ABLE
T
OMMAND
R/W
R/O
YPE
RxON Ch 1
17: L
EDUNDANCY
CR32
CR33
CR62
CR63
CR0
B
R/W
0
0
R
IT
0
EGISTER
IST AND
D
5
V
EFAULT
ALUE
C
RxON Ch 0
A
ONTROL
DDRESS
B
R/W
IT
0
Receiver Section ON - Channel 2
This READ/WRITE bit-field is used to either turn on or turn off the
Receive Section of Channel 2. If the user turns on the Receive Sec-
tion, then Channel 2 will begin to receive the incoming DS3, E3 or
STS-1 data-stream via the RTIP_2 and RRING_2 input pins.
Conversely, if the user turns off the Receive Section, then the entire
Receive Section (e.g., AGC and Receive Equalizer Block, Clock
Recovery PLL, etc) will be powered down.
0 - Shuts off the Receive Section of Channel 2.
1 - Turns on the Receive Section of Channel 2.
4
R
L
EGISTER
58
OCATIONS OF
T
R/W
R/W
R/O
R/O
R/O
Reserved
YPE
B
R/O
IT
0
- CR0 (A
3
G
APS/Redundancy Control Register
Block Level Interrupt Enable Register
Block Level Interrupt Status Register
Device/Part Number Register
Chip Revision Number Register
LOBAL
TxON Ch 2
DDRESS
D
B
R/W
ESCRIPTION
IT
0
R
2
EGISTERS
L
R
OCATION
EGISTER
TxON Ch 1
B
R/W
IT
0
= 0
N
1
AME
X
00)
XRT75R03
TxON Ch 0
REV. 1.0.8
B
R/W
IT
0
0