XRT75R03IVTR-F Exar Corporation, XRT75R03IVTR-F Datasheet - Page 86

• Manufacturer Part Number: XRT75R03IVTR-F
• Description: IC LIU E3/DS3/STS-1 3CH 128LQFP
• Manufacturer: Exar Corporation

Specifications of XRT75R03IVTR-F

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XRT75R03
REV. 1.0.8
B
IT
7 - 4
N
B
R/O
UMBER
3
2
IT
0
7
T
ABLE
JA RESET Ch_n
30: J
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
JA1 Ch_n
B
R/O
Unused
IT
0
N
ITTER
AME
6
Unused
A
TTENUATOR
B
R/O
IT
0
5
T
R/W
R/W
R/O
YPE
C
ONTROL
B
R/W
D
IT
0
V
EFAULT
ALUE
4
0
0
0
R
EGISTER
83
Jitter Attenuator RESET - Channel_n:
Writing a "0 to 1" transition within this bit-field will configure
the Jitter Attenuator (within Channel_n) to execute a
RESET operation.
Whenever the user executes a RESET operation, then all
of the following will occur.
•
•
N
Jitter Attenuator Configuration Select Input - Bit 1:
This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is
used to do any of the following.
•
•
The relationship between the settings of these two bit-
fields and the Enable/Disable States, and FIFO Depths is
presented below.
JA RESET
Channel 1 Address Location = 0x0F
Channel 2 Address Location = 0x17
OTE
The READ and WRITE pointers (within the Jitter
Attenuator FIFO) will be reset to their default values.
The contents of the Jitter Attenuator FIFO will be
flushed.
To enable or disable the Jitter Attenuator corresponding
to Channel_n.
To select the FIFO Depth for the Jitter Attenuator within
Channel_n.
Ch_n
B
R/W
- C
IT
0
: The user must follow up any "0 to 1" transition with
JA0
3
0
0
1
1
HANNEL
the appropriate write operate to set this bit-field
back to "0", in order to resume normal operation
with the Jitter Attenuator.
JA1
0
1
0
1
JA1 Ch_n
0 A
B
R/W
IT
0
DDRESS
2
D
Jitter Attenuator M ode
ESCRIPTION
FIFO Depth = 16 bits
FIFO Depth = 32 bits
JA in Tx Path
L
OCATION
Disabled
Disabled
Ch_n
B
R/W
IT
0
1
xr
xr
xr
xr
= 0
X
07
JA0 Ch_n
B
R/W
IT
0
0