XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 10

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XR17V352IB-0A-EVB

Manufacturer Part Number
XR17V352IB-0A-EVB
Description
EVAL BOARD FOR XR17V352 113BGA
Manufacturer
Exar Corporation

Specifications of XR17V352IB-0A-EVB

Main Purpose
Interface, UART
Embedded
-
Utilized Ic / Part
XR17V352
Primary Attributes
-
Secondary Attributes
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
0x6C-0x77 31:0
0x54-0x67 31:0
A
O
DDRESS
0x18h
0x1C
0x2C
0x3C
0x4C
0x7C
0x20
0x24
0x28
0x30
0x34
0x38
0x40
0x44
0x48
0x50
0x68
0x78
FFSET
31:0
31:0
31:0
31:0
31:0
31:16
15:0
31:0
31:8
7:0
31:0
31:24
23:16
15:8
7:0
31:0
31:0
31:0
31:0
31:16
15:8
7:0
31:16
15:8
7:0
31:16
15:8
7:0
31:0
B
ITS
EWR
EWR
RWR
T
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
T
YPE
ABLE
1: PCI L
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Unimplemented Base Address Register (returns zeros)
Reserved
Subsystem ID (write from external EEPROM by customer)
Subsystem Vendor ID (write from external EEPROM by cus-
tomer)
Expansion ROM Base Address (Unimplemented)
Reserved (returns zeros)
Capability Pointer
Reserved (returns zeros)
Unimplemented MAXLAT
Unimplemented MINGNT
Interrupt Pin, use INTA#.
Interrupt Line.
Not implemented or not applicable (return zeros)
CSR
Not implemented or not applicable (return zeros)
Not implemented or not applicable (return zeros)
64-bit address capable
Next Capability Pointer
MSI Capable Capability ID
Not implemented or not applicable (return zeros)
Not implemented or not applicable (return zeros)
Next Capability Pointer
MSI-X Capable Capability ID
Not implemented or not applicable (return zeros)
PME# support (PME# can be asserted from D3hot and D0)
PCI Power Management 1.2
Next Capability Pointer
Power Management Capability ID
No soft reset when transitioning from D3hot to D0 state
OCAL
B
US
C
ONFIGURATION
10
D
ESCRIPTION
S
PACE
R
EGISTERS
(
HEX OR BINARY
R
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x02106160
0x00000000
0x00000000
0x00000000
0x00000000
0x00000008
ESET
0x000000
0x0000
0x0000
0x0080
0x0000
0x4803
0xXX
0x50
0x00
0x00
0x01
0x05
0x01
0x78
0x78
0x11
0x80
REV. 1.0.1
V
ALUE
)

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