XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 16

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
The XR17V352 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is an 4-bit indicator representing both channels with each bit
representing each channel from 0 to 1. This permits the interrupt service routine to quickly determine which
UART channels need servicing so that it can go to the appropriate UART channel interrupt service routines.
INT0 bit [0] represents the interrupt status for UART channel 0 when its transmitter, receiver, line status, or
modem port status requires service. Other bits in the INT0 register provide indication for the other channels
with bit [1] representing UART channel 1 respectively.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1, INT2 and INT3 registers provide the 24-bit interrupt
status for both channels. bits [10:8] representing channel 0 and bits [13:11] representing channel 1
respectively. All other bits are reserved. Both channel interrupts status are available with a single DWORD read
operation. This feature allows the host another method to quickly service the interrupts, thus reducing the
service interval and host bandwidth requirement.
Note that the interrupts reported in this register is specific to each UART channel. If there is a global interrupt
such as the wake-up interrupt, timer/counter interrupt or MPIO interrupt, they would be reported in the 3-bit
code for channel 0 in INT1.
All bits start up zero. A special interrupt condition is generated by the V352 upon awakening from sleep after
both channels were put to sleep mode earlier. This wake-up interrupt is cleared by a read to the INT0 register.
Figure 4
0x0088-0x008B
0x008C-0x008F
0x0098-0x009B
0x0080
0x0084-0x0087
0x0090-0x0093
0x0094-0x0097
1.4.1
A
DDRESS
A
DDRESS
Ox098
Ox099
0x09A
0x09B
-
0x0083
shows the 4-byte interrupt register and its make up.
[A7:A0]
The Global Interrupt Registers - INT0, INT1, INT2 and INT3
GLOBAL INTERRUPT REGISTER (DWORD)
T
ANCILLARY1 (read/write)
ABLE
ANCILLARY2 (read-only)
T
INTERRUPT (read-only)
ABLE
INT3 [31:24]
TIMER (read/write)
MPIO1 (read/write)
MPIO2 (read/write)
MPIO3 (read/write)
MPIOSEL[15:8]
MPIOINV[15:8]
MPIOOD[15:8]
6: D
R
Reserved
5: D
R
EGISTER
EGISTER
EVICE
EVICE
C
C
ONFIGURATION
ONFIGURATION
Read/Write MPIO[15:8] input polarity select
Read/Write MPIO[15:8] select
Read/Write MPIO[15:8] open-drain output control
INT2 [23:16]
B
MPIOSEL[7:0]
MPIOINT[7:0]
MPIO3T[7:0]
TIMERMSB
YTE
Reserved
SLEEP
INT3
3 [31:24]
R
R
R
EGISTERS SHOWN IN
EAD
16
EGISTERS SHOWN IN
/W
RITE
INT1 [15:8]
MPIOLVL[15:8]
B
MPIOOD[15:8]
MPIOINV[7:0]
YTE
TIMERLSB
C
OMMENT
RESET
REGB
INT2
2 [23:16]
[default 0x00-00-00-00]
DWORD
BYTE
MPIOSEL[15:8]
MPIOINT[15:8]
INT0 [7:0]
B
MPIO3T[7:0]
ALIGNMENT
YTE
Reserved
4XMODE
ALIGNMENT
DVID
INT1
1 [15:8]
Bits [15:8] = 0xFF
Bits [15:8] = 0x00
Bits [15:8] = 0x00
RESET STATE
MPIOINV[15:8]
0x00
MPIOLVL[7:0]
MPIOOD[7:0]
B
TIMERCNTL
YTE
8XMODE
DREV
INT0
REV. 1.0.1
0 [7:0]