XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 44

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
SEE”RECEIVER” ON PAGE 42.
SEE”TRANSMITTER” ON PAGE 40.
DLM[7:0], DLL[7:0] and DLD[3:0]
The Baud Rate Generator (BRG) generates the data rate for the transmitter and receiver. The rate is
programmed through registers DLM, DLL and DLD which are only accessible when LCR bit [7] is set to logic 1.
Refer to
details.
DLD[7]: RS-485 Polarity
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•
DLD[6]: Multi-drop Mode
•
•
DLD[5]: XON/XOFF Parity Check
•
•
DLD[4]: Fast IR Mode
•
•
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR) and also
encoded in INT (INT0-INT3) register in the Device Configuration Registers.
When the receive FIFO (FCR bit [0] = logic 1) and receive interrupts (IER bit [0] = logic 1) are enabled, the
RHR interrupts (see ISR bits [4:3]) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
C. The receive data ready bit (LSR bit [0]) is set as soon as a character is transferred from the shift register to
4.0 UART CONFIGURATION REGISTERS
4.1
4.2
4.3
4.4
4.4.1
Logic 0 = The Auto RS-485 Half-duplex direction control pin will be HIGH for TX and LOW for RX.
Logic 1 = The Auto RS-485 Half-duplex direction control pin will be LOW for TX and HIGH for RX.
Logic 0 = Normal mode.
Logic 1 = Enable Multi-drop mode.
Logic 0 = XON/XOFF characters are valid flow control characters even if they have parity errors.
Logic 1 = XON/XOFF characters are not valid flow control characters if they have parity errors.
Logic 0 = If IR mode is enabled, IR pulsewidth will be 3/16th of bit time.
Logic 1 = If IR mode is enabled, IR pulsewidth will be 1/4th of bit time.
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
the receive FIFO. It is reset when the FIFO is empty.
Receive Holding Register (RHR) - Read only
Transmit Holding Register (THR) - Write only
Baud Rate Generator Divisors (DLM, DLL and DLD)
Interrupt Enable Register (IER) - Read/Write
“Section 3.1, Programmable Baud Rate Generator with Fractional Divisor” on page 31
IER versus Receive FIFO Interrupt Mode Operation
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REV. 1.0.1
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