XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 18

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
The XR17V352 has a general purpose 16-bit timer/counter. The internal 125MHz clock or the external clock at
the TMRCK input pin can be selected as the clock source for the timer/counter. The timer can be set to be a
single-shot for a one-time event or re-triggerable for a periodic signal. An interrupt may be generated when the
timer times out and will show up as a Channel 0 interrupt (see
registers [TIMERCNTL, TIMER, TIMELSB, TIMERMSB]. The TIMERCNTL register provides the Timer
commands such as start/stop, as shown in
optionally routed to the MPIO[0] pin. The block diagram of the Timer/Counter circuit is shown below:
TIMERMSB [31:24] and TIMERLSB [23:16] registers
The concatentaion of the 8-bit registers TIMERMSB and TIMERLSB forms a 16-bit value which decides the
time-out period of the Timer, per the following equation:
The least-significant bit of the timer is being bit [0] of the TIMERLSB with most-significant-bit being bit [7] in
TIMERMSB. Notice that these registers do not hold the current counter value when read. Default value is zero
(timer disabled) upon powerup and reset. The ’Reset Timer’ command does not have any effect on this
register.
Wake-up Indicator is cleared by reading the INT0 register.
RXRDY and RXRDY Time-out is cleared by reading data in the RX FIFO.
RX Line Status interrupt clears after reading the LSR register that is in the UART channel register set.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon delta and special character detect interrupt clears after reading the ISR register that is in the UART channel reg-
ister set.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
1.4.2
F
IGURE
COMMANDS
TIMERCNTL
125MHz/62.5MHz
0
General Purpose 16-bit Timer/Counter [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (
X
TIMERMSB and TIMERLSB
XX-XX-00-00)
5. T
Timer output frequency = Timer input clock / 16-bit Timer value
IMER
TMRCK
(16-bit Value)
/C
Clock Select
Start/Stop
Single shot/Re-triggerable
Route/De-route to MPIO[0]
Timer Interrupt Enable/ Disable
OUNTER CIRCUIT
T
ABLE
1
0
8: UART C
Timer/Counter
Table 9
HANNEL
16-Bit
18
below. The time-out output of the Timer can also be
[1:0] I
Timer Interrupt
NTERRUPT
MPIOLVL[0]
Table
Output
Timer
7). It is controlled through 4 configuration
1
0
C
LEARING
MPIO[0]
1
0
Timer Interrupt
No Interrupt
REV. 1.0.1
DEFAULT