XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 12

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

XR17V352
HIGH PERFORMANCE DUAL PCI EXPRESS UART
N
The V352 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The
EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This interface is provided
in order to program the registers in the PCI Configuration Space of the PCI UART during power-up. The
EEPROM must be organized into address/data pairs. The first word of the pair is the address and the second
word is the data.
Table 3
other Target Addresses are reserved and must not be used.
The second 16-bit word of the address/data pair is the data. The default values are shown in
address/data pairs can be in any order. Only the contents which need to be changed from the Exar defaults
need to be included in the EEPROM.
1.2
OTE
A
O
0x104-
DDRESS
0x113
0x114
FFSET
: EWR=Read/Write from external EEPROM. RWR=Read/Write. RO= Read Only. RWC=Read/Write-Clear.
EEPROM Interface
shows the Target Addresses available for programming into bits 7:0 of the 16-bit address word. All
T
31:0
31:0
ARGET
B
ITS
Table 2
0x00
0x01
0x02
0x03
0x04
0x05
B
A
13:8
7:0
IT
15
14
DDRESS
(
S
)
T
RO
RO
T
YPE
below shows the format of the 16-bit address:
ABLE
T
ABLE
1: PCI L
T
Not implemented or not applicable (return zeros)
VC Offset 0x4
ABLE
Parity Bit - Odd parity over entire address/data pair
If there is a parity error, it will be reported in bit-3 of the REGB register in
the Device Configuration Registers (offset 0x08E).
Final Address
If 1, this will be the last data to be read.
If 0, there will be more data to be read after this.
Reserved - Bits must be ’0’
Target Address - See
lower 8-bits are reserved
3: T
Subsystem Vendor ID
Class Code [23:8]
2: EEPROM A
Class Code [7:0]
OCAL
Subsystem ID
ARGET
Vendor ID
Device ID
D
ATA
B
US
A
DDRESS
C
ONFIGURATION
Table 3
DDRESS
12
D
F
ESCRIPTION
OR
D
B
EEPROM V
EFINITION
IT
0x13A8
0x0352
0x0200
0x0700
0x0000
0x0000
D
S
EFINITIONS
PACE
ALUES
R
E
EGISTERS
XAR
D
EFAULT
(
HEX OR BINARY
0x8000000FF
R
0x00000000
ESET
Table
REV. 1.0.1
V
ALUE
3. The
)