XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 47

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
•
]
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
ISR[5:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See
4.5.1, Interrupt Generation:” on page 46
ISR[0]: Interrupt Status
•
•
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
The FCTR bits [5:4] are associated with these 2 bits. These 2 bits are used to set the trigger level for the
receive FIFO. The UART will issue a receive interrupt when the number of the characters in the FIFO crosses
the trigger level.
different trigger tables. Whichever selection is made last applies to both the RX and TX side.
FCR[5:4]: Transmit FIFO Trigger Select (requires EFR bit [4]=1)
(logic 0 = default, TX trigger level = 1)
The FCTR bits [7:6] are associated with these 2 bits by selecting one of the four tables. The 4 user selectable
trigger levels in 4 tables are supported for compatibility reasons. These 2 bits set the trigger level for the
transmit FIFO interrupt. The UART will issue a transmit interrupt when the number of characters in the FIFO
falls below the selected trigger level, or when it gets empty in case that the FIFO did not get filled over the
trigger level on last re-load.
4.6
P
Wake-up indicator is cleared by a read to the INT0 register.
Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
Logic 1 = No interrupt pending. (default condition)
L
RIORITY
EVEL
X
1
2
3
4
5
6
7
FIFO Control Register (FCR) - Write Only
B
IT
0
0
0
0
0
0
1
0
[5]
Table 15
B
IT
0
0
0
0
0
1
0
0
[4]
ISR R
shows the complete selections. Note that the receiver and the transmitter cannot use
Table 15
B
IT
T
EGISTER
0
0
1
0
0
0
0
0
ABLE
[3]
B
14: I
below shows the selections.
S
IT
TATUS
1
1
1
0
0
0
0
0
[2]
NTERRUPT
and
B
B
ITS
IT
“Section 4.5.2, Interrupt Clearing:” on page 46
1
0
0
1
0
0
0
0
[1]
S
OURCE AND
47
B
HIGH PERFORMANCE DUAL PCI EXPRESS UART
IT
0
0
0
0
0
0
0
1
[0]
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
RXRDY (Received Xon/Xoff or Special character)
CTS#/DSR#, RTS#/DTR# change of state
None (default)
P
RIORITY
L
S
EVEL
OURCE OF THE INTERRUPT
Table
14). See
XR17V352
for details.
“Section