XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 17

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit [0] represents channel 0 and
bit [1] indicates channel 1. All other bits are reserved. Logic 1 indicates the channel N [1:0] has called for
service. The interrupt bit clears after reading the appropriate register of the interrupting channel register, see
Interrupt Clearing section.
INT3, INT2 and INT1 [31:8] 3-bit Channel Interrupt Encoding
Each channel’s interrupt is encoded into 3 bits for receive, transmit, and status. Bits [10:8] represent channel 0
and go up to channel 1 with bits [13:11]. The 3-bit encoding and their priority order are shown below in
The wake-up interrupt, timer/counter interrupt and MPIO interrupt are only reported in channel 0 of INT1
(bits[10:8]). These interrupts are not reported in any other location.
F
P
IGURE
RIORITY
1
2
3
4
5
6
7
0
x
Reserved
4. T
0
B
HE
0
IT
[
0
0
0
0
1
1
1
1
N
G
+2]
INT3 Register
0
LOBAL
Reserved
0
B
IT
I
T
[
NTERRUPT
0
0
1
1
0
0
1
1
N
ABLE
0
+1]
The INT0 register provides individual status for each channel
0
7: UART C
Reserved
B
0
IT
0
1
0
1
0
1
0
1
R
[
N
EGISTER
]
Bit-7
0
0
None or wake-up indicator (wake-up indicator is reported in channel 0 only)
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Reported in channel 0 only.
Timer/Counter. Reported in channel 0 only.
0
HANNEL
Bit-6
Individual UART Channel Interrupt Status
0
Reserved
, INT0, INT1, INT2
0
Bit-5
INT0, INT1, INT2 and INT3
0
INT2 Register
Interrupt Registers,
[1:0] I
INT0 Register
Bit-4
0
0
17
0
HIGH PERFORMANCE DUAL PCI EXPRESS UART
Bit-3 Bit-2 Bit-1 Bit-0
NTERRUPT
0
Reserved
0
0
AND
0
Ch-1 Ch-0
I
NTERRUPT
S
0
INT3
OURCE
Reserved
Bit-7 Bit-6 Bit-5
0
0
E
0
S
0
NCODING
OURCE
N+2
0
Bit
Channel-1
(
INT0 Register
Bit-4
S
N+1
Bit
0
INT1 Register
)
Bit-3 Bit-2 Bit-1
Bit
0
N
N+2
Bit
0
XR17V352
Channel-0
Ch-1
N+1
Bit
Bit-0
Ch-0
Bit
N
Table
7.