XR17V352IB-0A-EVB Exar Corporation, XR17V352IB-0A-EVB Datasheet - Page 29

• Manufacturer Part Number: XR17V352IB-0A-EVB
• Description: EVAL BOARD FOR XR17V352 113BGA
• Manufacturer: Exar Corporation

Specifications of XR17V352IB-0A-EVB

• Main Purpose: Interface, UART
• Embedded: -
• Utilized Ic / Part: XR17V352
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
The XR17V352 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x0200 (channel 0) and 0x0600 (channel 1). The entire RX data along with the status can
be downloaded in a single PCI Burst Read operation of 32 DWORD reads. The Status and Data bytes must be
read in 16 or 32 bits format to maintain data integrity. The following tables show this clearly.
The TX FIFO data (up to the maximum 256 bytes) can be loaded in a single burst 32-bit write operation
(maximum 16 DWORD writes) at memory locations 0x0100 (channel 0) and 0x0500 (channel 1).
2.1.2
2.1.3
Data Bit-31
Data Bit-31
WITH LSR
Read n+0 to n+1
Read n+2 to n+3
PCI Bus
Write n+0 to n+3
Write n+4 to n+7
PCI Bus
R
W
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
EAD
RITE
Etc.
RX FIFO,
Etc
Receive Data Byte n+1
Receive Data Byte n+3
TX FIFO
Special Rx FIFO Data Unloading at locations 0x0200 and 0x0600
Tx FIFO Data Loading at locations 0x100 and 0x500
E
RRORS
Channel 0 to 1 Receive Data with Line Status Register in 32-bit alignment through the Configuration
FIFO Data n+1
FIFO Data n+3
FIFO Data n+3
FIFO Data n+7
Channel 0 to 1 Receive Data in 32-bit alignment through the Configuration Register Address
B
B
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
YTE
YTE
Line Status Register n+1
3
3
Receive Data Byte n+2
Register Address 0x0200 and 0x0600
FIFO Data n+2
FIFO Data n+6
LSR n+1
LSR n+3
0x0100 and 0x0500
B
B
YTE
YTE
29
HIGH PERFORMANCE DUAL PCI EXPRESS UART
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
2
2
Receive Data Byte n+1
Receive Data Byte n+0
FIFO Data n+0
FIFO Data n+2
FIFO Data n+1
FIFO Data n+5
B
B
YTE
YTE
1
1
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+0
Receive Data Byte n+0
FIFO Data n+0
FIFO Data n+4
XR17V352
LSR n+0
LSR n+2
B
B
YTE
YTE
Data Bit-0
Data Bit-0
PCI Bus
0
0
PCI Bus