FDMS7672AS Fairchild Semiconductor, FDMS7672AS Datasheet - Page 2

• Manufacturer Part Number: FDMS7672AS
• Description: MOSFET N-CH 30V SYNCFET POWER56
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®, SyncFET™r

Specifications of FDMS7672AS

• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 4 mOhm @ 18A, 10V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 19A
• Vgs(th) (max) @ Id: 3V @ 1mA
• Gate Charge (qg) @ Vgs: 46nC @ 10V
• Input Capacitance (ciss) @ Vds: 2820pF @ 15V
• Power - Max: 2.5W
• Mounting Type: Surface Mount
• Package / Case: 8-PQFN, Power56
• Configuration: Single
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 4.3 m Ohms
• Forward Transconductance Gfs (max / Min): 97 S
• Drain-source Breakdown Voltage: 30 V
• Continuous Drain Current: 42 A
• Power Dissipation: 45 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FDMS7672AS Rev.C
Notes:
1. R
2. Pulse Test: Pulse Width < 300 µs, Duty cycle < 2.0%.
3. E
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
Electrical Characteristics
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
BV
∆BV
I
I
V
r
g
C
C
C
R
t
t
t
t
Q
Q
Q
Q
V
t
Q
∆V
DSS
GSS
d(on)
r
d(off)
f
rr
DS(on)
FS
the user's board design.
GS(th)
SD
iss
oss
rss
g
∆T
∆T
g
g
gs
gd
rr
Symbol
θJA
AS
DSS
GS(th)
DSS
J
J
of 60 mJ is based on starting T
is determined with the device mounted on a 1in
Drain to Source Breakdown Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate to Source Leakage Current, Forward
Gate to Source Threshold Voltage
Gate to Source Threshold Voltage
Temperature Coefficient
Static Drain to Source On Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Gate Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Total Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
Source to Drain Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
(Note 2)
J
= 25
Parameter
°
C, L = 1 mH, I
2
T
a. 50 °C/W when mounted on a
pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. R
J
1 in
= 25 °C unless otherwise noted
AS
2
= 11 A, V
pad of 2 oz copper.
DD
= 27 V, V
V
V
V
V
V
f = 1 MHz
V
I
V
V
V
V
V
V
V
I
I
I
V
V
D
F
D
D
DD
GS
GS
GS
GS
GS
GS
GS
GS
DS
DS
GS
GS
DS
GS
= 18 A, di/dt = 300 A/µs
= 10 mA, referenced to 25 °C
= 1 mA, V
= 10 mA, referenced to 25 °C
GS
= 15 V, V
= 15 V, I
= 10 V, R
= 0 V to 10 V
= 0 V to 4.5 V
= 5 V, I
= 0 V, I
= 0 V, I
= 24 V, V
= V
= 10 V, I
= 7 V, I
= 4.5 V, I
= 10 V, I
= 20 V, V
= 10 V. 100% test at L = 0.3 mH, I
2
DS
Test Conditions
, I
D
D
S
S
D
GS
D
D
D
= 2 A
= 18 A
D
= 18 A
= 16 A
GS
GEN
GS
DS
= 1 mA
= 18 A,
= 18 A
= 18 A, T
= 14 A
= 0 V
= 0 V,
= 0 V
= 0 V
= 6 Ω
V
I
D
DD
= 18 A
J
= 15 V,
= 125 °C
(Note 2)
(Note 2)
θJC
AS
is guaranteed by design while R
= 16 A.
b. 125 °C/W when mounted on a
Min
1.2
minimum pad of 2 oz copper.
30
2120
0.48
0.80
735
1.1
Typ
1.9
3.2
3.5
4.3
4.1
90
6.5
4.0
26
26
97
12
28
33
15
-5
18
5
4
2820
Max
975
135
2.2
0.9
1.3
θCA
500
100
3.0
4.0
4.5
5.2
5.2
42
42
21
10
44
10
46
22
www.fairchildsemi.com
is determined by
mV/°C
mV/°C
Units
mΩ
nC
pF
pF
pF
µA
nA
nC
nC
nC
nC
ns
Ω
ns
ns
ns
ns
V
V
S
V