S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 207

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The trigger priorities described in
on the lower channel number (0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to
final state has priority over all other matches.
6.3.2.7.4
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features four flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further triggers on the same channel have no affect.
6.3.2.8
Each comparator has a bank of registers that are visible through an 8-byte window in the S12XDBG
module register address map. Comparators A and C consist of 8 register bytes (3 address bus compare
registers, two data bus compare registers, two data bus mask registers and a control register).
Freescale Semiconductor
Address: 0x0027
SC[3:0]
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Reset
W
R
Comparator Register Descriptions
0
0
7
Debug Match Flag Register (DBGMFR)
Match2 triggers to State2....... Match0 triggers to Final State....... Other matches have no effect
Match3 triggers to State2....... Match1 triggers to Final State....... Other matches have no effect
Match0 triggers to Final State.......Match1 triggers to State1...Other matches have no effect
Match1 triggers to State1....... Match3 triggers to State2....... Other matches have no effect
= Unimplemented or Reserved
0
0
6
Table 6-24. State3 — Sequencer Next State Selection
Figure 6-12. Debug Match Flag Register (DBGMFR)
Match1 triggers to Final State....... Other matches have no effect
Match2 triggers to Final State....... Other matches have no effect
Match3 triggers to Final State....... Other matches have no effect
Match0 triggers to State1....... Other matches have no effect
Match1 triggers to State1....... Other matches have no effect
Match0 triggers to State2....... Other matches have no effect
Match1 triggers to State2....... Other matches have no effect
S12XS Family Reference Manual, Rev. 1.11
Reserved. (No match triggers state sequencer transition)
Reserved. (No match triggers state sequencer transition)
Table 6-39
0
0
5
Any match triggers to Final State
dictate that in the case of simultaneous matches, the match
0
0
4
Description
MC3
0
3
MC2
0
2
S12X Debug (S12XDBGV3) Module
MC1
0
1
MC0
0
0
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