S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 466

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer Module (TIM16B8CV2)
16.2.7
This pin serves as input capture or output compare for channel 1.
16.2.8
This pin serves as input capture or output compare for channel 0.
16.3
This section provides a detailed description of all memory and registers.
16.3.1
The memory map for the TIM16B8CV2 module is given below in
register is the address offset. The total address for each register is the sum of the base address for the
TIM16B8CV2 module and the address offset for each register.
16.3.2
466
This section consists of register descriptions in address order. Each description includes a standard
register diagram with an associated figure number. Details of register bit and field function follow the
register diagrams, in bit order.
Register
CFORC
TCNTH
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
TCNTL
OC7M
Name
OC7D
TIOS
Memory Map and Register Definition
IOC1 — Input Capture and Output Compare Channel 1 Pin
IOC0 — Input Capture and Output Compare Channel 0 Pin
Module Memory Map
Register Descriptions
For the description of interrupts see
W
W
W
W
W
W
R
R
R
R
R
R
TCNT15
Figure 16-5. TIM16B8CV2 Register Summary (Sheet 1 of 3)
OC7M7
OC7D7
TCNT7
FOC7
IOS7
Bit 7
0
= Unimplemented or Reserved
TCNT14
OC7M6
OC7D6
TCNT6
S12XS Family Reference Manual, Rev. 1.11
FOC6
IOS6
6
0
TCNT13
OC7M5
OC7D5
TCNT5
FOC5
IOS5
5
0
NOTE
Section 16.6,
TCNT12
OC7M4
OC7D4
TCNT4
FOC4
IOS4
4
0
TCNT11
OC7M3
OC7D3
TCNT3
FOC3
IOS3
Figure
“Interrupts”.
3
0
16-5. The address listed for each
TCNT10
OC7M2
OC7D2
TCNT2
FOC2
IOS2
2
0
OC7M1
Freescale Semiconductor
OC7D1
TCNT9
TCNT1
FOC1
IOS1
1
0
OC7M0
OC7D0
TCNT8
TCNT0
FOC0
IOS0
Bit 0
0