S9S12XS128J1MAL Freescale Semiconductor, S9S12XS128J1MAL Datasheet - Page 723

• Manufacturer Part Number: S9S12XS128J1MAL
• Description: IC MCU 16BIT 128KB FLSH 112LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of S9S12XS128J1MAL

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 91
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 8K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.72 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 112-LQFP
• Processor Series: S12XS
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 8 KB
• Interface Type: CAN, SCI, SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 91
• Number Of Timers: 12
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: DEMO9S12XSFAME, EVB9S12XEP100
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

0x0140–0x017F MSCAN (CAN0) Map (continued)
Freescale Semiconductor
Address
0x015C-
0x0150-
0x0154-
0x0158-
0x0160-
0x0170-
0x014C
0x014D
0x0142
0x0143
0x0144
0x0145
0x0146
0x0147
0x0148
0x0149
0x014A
0x014B
0x014E CAN0RXERR
0x014F
0x0153
0x0157
0x015B
0x015F
0x016F
0x017F
CAN0IDMR0-
CAN0IDMR4-
CAN0TXERR
CAN0TBSEL
CAN0IDAR0-
CAN0IDAR4-
CAN0IDMR3
CAN0IDMR7
CAN0IDAR3
CAN0IDAR7
CAN0RXFG
CAN0RFLG
CAN0TARQ
CAN0TXFG
CAN0BTR0
CAN0BTR1
CAN0TFLG
CAN0MISC
CAN0RIER
CAN0TAAK
CAN0TIER
CAN0IDAC
Reserved
Name
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
R
R
R
R
R RXERR7
R TXERR7
R
R
R
R
R
R
WUPIF
WUPIE
SAMP
SJW1
Bit 7
AM7
AM7
AC7
AC7
0
0
0
0
0
0
0
0
S12XS Family Reference Manual, Rev. 1.11
(See
(See
RXERR6
TXERR6
TSEG22
CSCIF
CSCIE
SJW0
Bit 6
AM6
AM6
AC6
AC6
0
0
0
0
0
0
0
0
Detailed MSCAN Foreground Receive and Transmit Buffer
Detailed MSCAN Foreground Receive and Transmit Buffer
RSTATE1
RXERR5
TXERR5
TSEG21
RSTAT1
IDAM1
BRP5
Bit 5
AM5
AM5
AC5
AC5
FOREGROUND TRANSMIT BUFFER
0
0
0
0
0
0
0
FOREGROUND RECEIVE BUFFER
RSTATE0
RXERR4
TSEG20
TXERR4
RSTAT0
IDAM0
BRP4
Bit 4
AM4
AM4
AC4
AC4
0
0
0
0
0
0
0
TSTATE1
RXERR3
TXERR3
TSEG13
TSTAT1
BRP3
Bit 3
AM3
AM3
AC3
AC3
0
0
0
0
0
0
0
0
TSTATE0
ABTRQ2
RXERR2
TXERR2
TSEG12
ABTAK2
TSTAT0
TXEIE2
IDHIT2
BRP2
TXE2
Bit 2
AM2
AM2
TX2
AC2
AC2
0
0
Detailed Register Address Map
RXERR1
ABTRQ1
TXERR1
TSEG11
ABTAK1
TXEIE1
IDHIT1
OVRIF
OVRIE
BRP1
TXE1
Bit 1
AM1
AM1
TX1
AC1
AC1
Layout)
Layout)
0
0
BOHOLD
RXERR0
ABTRQ0
TXERR0
TSEG10
ABTAK0
TXEIE0
IDHIT0
RXFIE
BRP0
TXE0
Bit 0
AM0
AM0
RXF
TX0
AC0
AC0
0
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