A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 118

• Manufacturer Part Number: A2F200M3F-1FGG256
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG256

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
JTAG Pins
5 - 8
Name
JTAGSEL
TCK
TDI
TDO
TMS
TRSTB
Type
SmartFusion devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run at
any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
SmartFusion part must be supplied to allow JTAG signals to transition the SmartFusion device. Isolating
the JTAG power supply in a separate I/O bank gives greater flexibility with supply selection and simplifies
power supply and PCB design. If the JTAG interface is neither used nor planned to be used, the VJTAG
pin together with the TRSTB pin could be tied to GND.
Out
In
In
In
Bus Size
Polarity/
HIGH
HIGH
1
1
1
1
JTAG controller selection
Depending on the state of the JTAGSEL pin, an external JTAG controller will either
see the FPGA fabric TAP/auxiliary TAP (High) or the Cortex-M3 JTAG debug
interface (Low).
The JTAGSEL pin should be connected to an external pull-up resistor such that the
default configuration selects the FPGA fabric TAP.
Test clock
Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have
an internal pull-up/-down resistor. If JTAG is not used, it is recommended to tie off
TCK to GND or V
JTAG operation in case TMS enters an undesired state.
Note that to operate at all V
Refer to
Test data
Serial input for JTAG boundary scan, ISP, and UJTAG usage. There is an internal
weak pull-up resistor on the TDI pin.
Serial output for JTAG boundary scan, ISP, and UJTAG usage.
Test mode select
The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO,
TRST). There is an internal weak pull-up resistor on the TMS pin.
Boundary scan reset pin
The TRST pin functions as an active low input to asynchronously initialize (or reset)
the boundary scan circuitry. There is an internal weak pull-up resistor on the TRST
pin. If JTAG is not used, an external pull-down resistor could be included to ensure
the TAP is held in reset mode. The resistor values must be chosen from
page 5-9
Table 5-1 on page 5-9
is used. The values correspond to the equivalent parallel resistor when multiple
devices are connected via a JTAG chain.
In critical applications, an upset in the JTAG circuit could allow entering an undesired
JTAG state. In such cases, it is recommended that you tie off TRST to GND through
a resistor placed close to the FPGA pin.
The TRSTB pin also resets the serial wire JTAG – debug port (SWJ-DP) circuitry
within the Cortex-M3.
Test data
Table 5-1 on page 5-9
and must satisfy the parallel resistance value requirement. The values in
JTAG
through a resistor placed close to the FPGA pin. This prevents
correspond to the resistor recommended when a single device
R e vi s i o n 6
JTAG
for more information.
voltages, 500 Ω to 1 kΩ will satisfy the requirements.
Description
Table 5-1 on