A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 70
A2F200M3F-1FGG256
Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet
1.A2F500M3G-FGG256.pdf
(192 pages)
Specifications of A2F200M3F-1FGG256
Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Price
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Part Number:
A2F200M3F-1FGG256
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Part Number:
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Quantity:
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SmartFusion DC and Switching Characteristics
Figure 2-26 • Timing Model and Waveforms
Table 2-78 • Register Delays
2- 58
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
CLK
Data
EN
Out
CLKQ
SUD
HD
SUE
HE
CLR2Q
PRE2Q
REMCLR
RECCLR
REMPRE
RECPRE
WCLR
WPRE
CKMPWH
CKMPWL
PRE
CLR
For specific junction temperature and voltage supply levels, refer to
Worst Commercial-Case Conditions: T
Timing Characteristics
Clock-to-Q of the Core Register
Data Setup Time for the Core Register
Data Hold Time for the Core Register
Enable Setup Time for the Core Register
Enable Hold Time for the Core Register
Asynchronous Clear-to-Q of the Core Register
Asynchronous Preset-to-Q of the Core Register
Asynchronous Clear Removal Time for the Core Register
Asynchronous Clear Recovery Time for the Core Register
Asynchronous Preset Removal Time for the Core Register
Asynchronous Preset Recovery Time for the Core Register
Asynchronous Clear Minimum Pulse Width for the Core Register
Asynchronous Preset Minimum Pulse Width for the Core Register
Clock Minimum Pulse Width High for the Core Register
Clock Minimum Pulse Width Low for the Core Register
50%
50%
t
SUE
t
HE
50%
t
CLKQ
50%
t
SUD
0
t
HD
t
PRE2Q
50%
50%
50%
Description
t
WPRE
50%
50%
J
= 85°C, Worst-Case VCC = 1.425 V
50%
t
t
RECPRE
WCLR
R e visio n 6
50%
t
50%
50%
CLR2Q
50%
t
RECCLR
Table 2-7 on page 2-9
50%
t
CKMPWH
t
50%
REMPRE
0.56
0.44
0.00
0.46
0.00
0.41
0.41
0.00
0.23
0.00
0.23
0.22
0.22
0.32
0.36
–1
for derating values.
t
CKMPWL
50%
0.67
0.00
0.55
0.00
0.49
0.49
0.00
0.27
0.00
0.27
0.22
0.22
0.32
0.36
Std.
0.52
50%
50%
t
REMCLR
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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