A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 186

• Manufacturer Part Number: A2F200M3F-1FGG256
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG256

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
6 - 4
Revision
Revision 3
(continued)
A note was added to
f
limited to 100 MHz (maximum) by software" (SAR 26388).
Table 2-88 • eNVM Block Timing, Worst Commercial Case Conditions: T
VCC = 1.425 V
Std. speed grades. A note was added to define 6:1:1:1 and 5:1:1:1 (SAR 26166).
The units were corrected (mV instead of V) for input referred offset voltage, GDEC[1:0]
= 00 in
The test condition values for operating current (ICC33A, typical) were changed in
Table 2-97 • Voltage Regulator
Figure 2-44 • Typical Output Voltage
stating the load represented by each (SAR 25247).
The
SmartFusion Subsystem Microcontroller User’s Guide (SAR 26542). The
Programming and Erase Times" section
Figure 4-1 • TRSTB Logic
nominal)" (SAR 24694).
Two notes were added to the
1. The following supplies should be connected together while following proper noise
2. The following 1.5 V supplies should be connected together while following proper noise
The descriptions for the "VCC33N", "NCAP", and
information on what to do if analog SCB features and SDDs are not used (SAR
26744).
Information was added to the
GPIO pins. The IO portion of the table was revised to state that unused I/O pins are
disabled by Libero IDE software and include a weak pull-up resistor (SAR 26890).
Information was added regarding behavior of used I/O pins during power-up.
The type for
A note was added to the
inputs should be grounded (SAR 26744).
The
27044).
The
Unused" information (SAR 27709).
out_CCC
filtering practices: VCC33A, VCC33ADCx, VCC33AP, VCC33SDDx, VCCMAINXTAL,
and VCCLPXTAL.
filtering practices: VCC, VCC15A, and VCC15ADCx.
"288-Pin CSP" section
"SmartFusion Programming"
"256-Pin FBGA"
Table 2-94 • ABPS Performance Specifications
, stating that "one of the CCC outputs (GLA0) is used as an MSS clock and is
"EMC_RW_N"
was revised. Values were included for A2F200 and A2F500, for –1 and
Table 2-84 • SmartFusion CCC/PLL
pin table was replaced and now includes "Handling When
"Analog Front-End (AFE)" table
was changed from In/out to Out (SAR 25113).
was revised to change 1.5 V to "VJTAG (1.5 V to 3.3 V
is new, with pin tables for A2F200 and A2F500 (SAR
"Supply Pins" table
"User Pins"
(SAR 26465).
chapter was moved to this document from the
was revised to add legends for the three curves,
Changes
R e vi s i o n 6
was added to this chapter.
table regarding tristating of used and unused
(SAR 27109):
"PCAP"
(SAR 25381).
pins were revised to include
stating that unused analog
Specification, pertaining to
J
= 85°C,
"Typical
5-2, 5-6,
Page
2-63
2-73
2-79
2-84
2-85
5-10
5-12
5-16
5-40
4-5
4-6
5-1
5-7
5-5