A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 121

• Manufacturer Part Number: A2F200M3F-1FGG256
• Description: FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
• Manufacturer: Actel

Specifications of A2F200M3F-1FGG256

• Processor Series: A2F200
• Core: ARM Cortex M3
• Number Of Logic Blocks: 8
• Maximum Operating Frequency: 120 MHz
• Number Of Programmable I/os: 117
• Data Ram Size: 4608 bit
• Delay Time: 200 ns
• Supply Voltage (max): 3.6 V
• Supply Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 200000
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Name
SPI_1_DO
SPI_1_SS
Universal Asynchronous Receiver/Transmitter (UART) Peripherals
UART_0_RXD
UART_0_TXD
UART_1_RXD
UART_1_TXD
Ethernet MAC
MAC_CLK
MAC_CRSDV
MAC_MDC
MAC_MDIO
MAC_RXDx
MAC_RXER
MAC_TXDx
MAC_TXEN
In/Out
Type
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
In
Bus Size
Polarity/
HIGH
HIGH
Rise
High
Rise
1
1
1
1
1
1
1
2
2
Data output. Second SPI.
Can also be used as an MSS GPIO (see
Slave select (chip select). Second SPI.
Can also be used as an MSS GPIO (see
Receive data. First UART.
Can also be used as an MSS GPIO (see
Transmit data. First UART.
Can also be used as an MSS GPIO (see
Receive data. Second UART.
Can also be used as an MSS GPIO (see
Transmit data. Second UART.
Can also be used as an MSS GPIO (see
Receive clock. 50 MHz ± 50 ppm clock source received from RMII PHY.
Carrier sense/receive data valid for RMII PHY
Can also be used as an FPGA User IO (see
RMII management clock
Can also be used as an FPGA User IO (see
RMII management data input/output
Can also be used as an FPGA User IO (see
Ethernet MAC receive data. Data recovered and decoded by PHY. The
RXD[0] signal is the least significant bit.
Can also be used as an FPGA User I/O (see
Ethernet MAC receive error. If MACRX_ER is asserted during reception,
the frame is received and status of the frame is updated with
MACRX_ER.
Can also be used as an FPGA user I/O (see
Ethernet MAC transmit data. The TXD[0] signal is the least significant
bit.
Can also be used as an FPGA user I/O (see
Ethernet MAC transmit enable. When asserted, indicates valid data for
the PHY on the TXD port.
Can also be used as an FPGA User I/O (see
R e v i s i o n 6
SmartFusion Intelligent Mixed Signal FPGAs
Description
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"GPIO_x" on page
"IO" on page
"IO" on page
"IO" on page
"IO" on page
"IO" on page
"IO" on page
"IO" on page
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