A2F200M3F-1FGG256 Actel, A2F200M3F-1FGG256 Datasheet - Page 30
A2F200M3F-1FGG256
Manufacturer Part Number
A2F200M3F-1FGG256
Description
FPGA - Field Programmable Gate Array 200K System Gates SmartFusion
Manufacturer
Actel
Datasheet
1.A2F500M3G-FGG256.pdf
(192 pages)
Specifications of A2F200M3F-1FGG256
Processor Series
A2F200
Core
ARM Cortex M3
Number Of Logic Blocks
8
Maximum Operating Frequency
120 MHz
Number Of Programmable I/os
117
Data Ram Size
4608 bit
Delay Time
200 ns
Supply Voltage (max)
3.6 V
Supply Current
3 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
A2F-Eval-Kit, A2F-Dev-Kit, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
200000
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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SmartFusion DC and Switching Characteristics
2- 18
Microcontroller Subsystem Dynamic Contribution—P
Guidelines
Toggle Rate Definition
A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage. If the
toggle rate of a net is 100%, this means that the net switches at half the clock frequency. Below are some
examples:
Enable Rate Definition
Output enable rate is the average percentage of time during which tristate outputs are enabled. When
non-tristate output buffers are used, the enable rate should be 100%.
Table 2-16 • Toggle Rate Guidelines Recommended for Power Calculation
Table 2-17 • Enable Rate Guidelines Recommended for Power Calculation
Component
α
α
Component
β
β
β
β
1
2
3
4
1
2
SoC Mode
P
•
•
MSS
The average toggle rate of a shift register is 100%, as all flip-flop outputs toggle at half of the
clock frequency.
The average toggle rate of an 8-bit counter is 25%:
– Bit 0 (LSB) = 100%
– Bit 1 = 50%
– Bit 2 = 25%
– …
– Bit 7 (MSB) = 0.78125%
– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . 0.78125%) / 8.
= P
AC22
I/O output buffer enable rate
FPGA fabric SRAM enable rate for read
operations
FPGA fabric SRAM enable rate for write
operations
eNVM enable rate for read operations
Toggle rate of VersaTile outputs
I/O buffer toggle rate
Definition
R e visio n 6
Definition
MSS
Toggle rate of the logic driving the
output buffer
Guideline
12.5%
12.5%
< 5%
Guideline
10%
10%
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