LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 137

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Use of the Pre-Map Preference Editor
Clock preferences can be set in the Pre-Map Preference Editor. Figure 9-12 shows an example screen shot. The
Pre-Map Preference Editor is a part of the ispLEVER Design Planner.
Figure 9-12. Pre-Map Preference Editor Example
Clock Dividers (CLKDIV)
The clock divider divides the high-speed clock by 1, 2, 4 or 8. All the outputs have matched input to output delay.
CLKDIV can take as its input the edge clocks and the CLKOP of the PLL. The divided outputs drive the primary
clock and are also available for general routing or secondary clocks. The clock dividers are used for providing the
low speed FPGA clocks for shift registers (x2, x4, x8) and DDR/SPI4 I/O logic interfaces.
CLKDIV Primitive Definition
Users can instantiate CLKDIV in the source code as defined in this section. Figure 9-13 and Tables 9-8 and 9-9
describe the CLKDIVB definitions.
Figure 9-13. CLKDIV Primitive Symbol
CLKI
RST
RELEASE
CLKDIVB
9-15
CDIV1
CDIV2
CDIV4
CDIV8
LatticeXP2 sysCLOCK PLL
Design and Usage Guide