LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 176

FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd

LFXP2-8E-5FTN256C

Manufacturer Part Number
LFXP2-8E-5FTN256C
Description
FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet

Specifications of LFXP2-8E-5FTN256C

Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Lattice Semiconductor
Figures 10-25 to 10-28 show the similar waveforms for the FIFO with output register and with output register enable
with RdEn. It should be noted that flags are asserted and de-asserted with similar timing to the FIFO without output
registers. However, it is only the data out 'Q' that is delayed by one clock cycle.
Figure 10-25. FIFO with Output Registers, Start of Data Write Cycle
Figure 10-26. FIFO with Output Registers, End of Data Write Cycle
Almost Full
Almost
Almost
Empty
Empty
Reset
Clock
WrEn
RdEn
Almost
Data
Empty
Empty
Reset
Full
Full
Clock
WrEn
RdEn
Data
Full
Q
Q
Invalid Data
Data_1
Data_N-2
Data_2
Data_N-1
10-26
Invalid Q
Data_3
Invalid Q
Data_N
Data_4
Data_X
LatticeXP2 Memory Usage Guide
Data_5
Data_X

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