LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 182
![FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-8E-5FTN256C
Manufacturer Part Number
LFXP2-8E-5FTN256C
Description
FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5FTN256C
Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5FTN256C
Manufacturer:
Lattice
Quantity:
63
Company:
Part Number:
LFXP2-8E-5FTN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 10-33 show the behavior of non-pipelined FIFO_DC or FIFO_DC without output registers. When we pipeline
the registers, the output data is delayed by one clock cycle. There is an extra option for the output registers to be
enabled by the RdEn signal.
Figures 10-34 to 10-37 show the similar waveforms for the FIFO_DC with output register and without output regis-
ter enable with RdEn. Note that flags are asserted and de-asserted with similar timing to the FIFO_DC without out-
put registers. However, it is only the data out 'Q' that is delayed by one clock cycle.
Figure 10-34. FIFO_DC with Output Registers, Start of Data Write Cycle
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Invalid Data
Data_1
Data_2
10-32
Invalid Q
Data_3
Data_4
LatticeXP2 Memory Usage Guide
Data_5
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