LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 34
![FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-8E-5FTN256C
Manufacturer Part Number
LFXP2-8E-5FTN256C
Description
FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5FTN256C
Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5FTN256C
Manufacturer:
Lattice
Quantity:
63
Company:
Part Number:
LFXP2-8E-5FTN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
• In the ‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle.
• In the ‘Add/Sub’ option the Accumulator can be switched between addition and subtraction on every cycle.
• The loading of operands can switch between parallel and serial operations.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-20 shows the MULT sysDSP element.
Figure 2-20. MULT sysDSP Element
Multiplicand
Multiplier
Signed A
Signed B
Shift Register B Out
Shift Register B In
n
Input Data
Register B
n
n
n
Register
Register
Input
Input
m
Register A
Input Data
m
m
Shift Register A Out
m
Shift Register A In
2-20
Multiplier
Multiplier
m
n
To
To
Multiplier
Register
Pipeline
x
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
(default)
LatticeXP2 Family Data Sheet
m+n
m+n
Output
Architecture
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