LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 276

• Manufacturer Part Number: LFXP2-8E-5FTN256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-5FTN256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Lattice XP2 sysDSP Usage Guide
parameter REG_INPUTA0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTA0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTA0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTA1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTA1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTA1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTB0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTB0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTB0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_INPUTB1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_INPUTB1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_INPUTB1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_PIPELINE0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_PIPELINE0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_PIPELINE0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_PIPELINE1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_PIPELINE1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_PIPELINE1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_OUTPUT_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_OUTPUT_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_OUTPUT_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDA_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDA_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDA_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDA_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDA_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDA_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDB_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDB_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDB_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_SIGNEDB_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_SIGNEDB_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_SIGNEDB_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB_0_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB_0_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB_0_RST = “ RST0, RST1, RST2, RST3 “;
parameter REG_ADDNSUB_1_CLK = “ NONE, CLK0, CLK1, CLK2, CLK3 “;
parameter REG_ADDNSUB_1_CE = “ CE0, CE1, CE2, CE3 “;
parameter REG_ADDNSUB_1_RST = “ RST0, RST1, RST2, RST3 “;
parameter GSR = “ Enabled, Disabled “;
MULT18X18ADDSUBSUMB
input A017,A016,A015,A014,A013,A012,A011,A010,A09;
input A08,A07,A06,A05,A04,A03,A02,A01,A00;
input A117,A116,A115,A114,A113,A112,A111,A110,A19;
input A18,A17,A16,A15,A14,A13,A12,A11,A10;
input A217,A216,A215,A214,A213,A212,A211,A210,A29;
input A28,A27,A26,A25,A24,A23,A22,A21,A20;
input A317,A316,A315,A314,A313,A312,A311,A310,A39;
input A38,A37,A36,A35,A34,A33,A32,A31,A30;
input B017,B016,B015,B014,B013,B012,B011,B010,B09;
input B08,B07,B06,B05,B04,B03,B02,B01,B00;
input B117,B116,B115,B114,B113,B112,B111,B110,B19;
input B18,B17,B16,B15,B14,B13,B12,B11,B10;
input B217,B216,B215,B214,B213,B212,B211,B210,B29;
input B28,B27,B26,B25,B24,B23,B22,B21,B20;
input B317,B316,B315,B314,B313,B312,B311,B310,B39;
input B38,B37,B36,B35,B34,B33,B32,B31,B30;
input SIGNEDA, SIGNEDB,ADDNSUB1,ADDNSUB3;
input SOURCEA0, SOURCEA1, SOURCEA2, SOURCEA3;
input SOURCEB0, SOURCEB1, SOURCEB2, SOURCEB3;
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