LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 321
![FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-8E-5FTN256C
Manufacturer Part Number
LFXP2-8E-5FTN256C
Description
FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5FTN256C
Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-8E-5FTN256C
Manufacturer:
Lattice
Quantity:
63
Company:
Part Number:
LFXP2-8E-5FTN256C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Methods 3 and 4 are of no interest as far as field upgrade is concerned. Therefore, this document will focus only on
methods 1 and 2.
Figure 17-3. Four Methods for Programming the SPI Flash Device
Definitions
SPI
SPI stands for the Serial Peripheral Interface defined originally by Motorola.
Master SPI
The FPGA device boots itself by acting as the SPI host to clock bitstream data out of the external SPI Flash device.
SDM (Self Download Mode)
The FPGA device boots itself in a massive parallel fashion from the embedded Flash for instant-on.
Erase
Write into all the Flash cells state a logical one (1) (a.k.a. open fuse).
Program
Write into the selected Flash cells state a logical zero (0) (a.k.a. close fuse).
Configure
Write the pattern into the SRAM fuses of the FPGA device and wake up. It is also known as boot up.
Primary Boot
Upon power cycling, the FPGA device will load this pattern in first. Only one primary pattern is allowed.
Golden Boot
The guaranteed good pattern loaded into the FPGA device when booting failure occurs. It is also known as the root
boot. Only one Golden boot pattern is allowed.
4. Use off board programming method such as the third party programmers from BPM Microsystems or Sys-
1
2
tem General to pre-program the SPI Flash devices and then mount them on board.
ispVME
CPU
System
ispVM
TCK
TDI
TMS
TDO
JTAG
SHIFT_DR_CSN
SHIFT_DR_TDO
SHIFT_DR_TCK
SHIFT_DR_TDI
LatticeXP2
17-3
CSSPIN
PROGRAM_SPI
IO
IO
IO
3
1
2
1
0
LatticeXP2 Dual Boot Feature
CCLK
SISPI
CSSPIN
SPISO
Note:
The CSSPIN pin is dedicated when the
CFGO pin is set to 0 to enable the dual
boot feature.
Driver
CPU
SPI
SCLK
4 GPIO
CSN
SO
SI
Flash
SPI
4
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