LFXP2-8E-5FTN256C Lattice, LFXP2-8E-5FTN256C Datasheet - Page 313
![FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-8E-5FTN256C
Manufacturer Part Number
LFXP2-8E-5FTN256C
Description
FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -5 Spd
Manufacturer
Lattice
Datasheet
1.LFXP2-8E-5FTN256I.pdf
(341 pages)
Specifications of LFXP2-8E-5FTN256C
Number Of Macrocells
8000
Number Of Programmable I/os
201
Data Ram Size
226304
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FTBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Part Number:
LFXP2-8E-5FTN256C
Manufacturer:
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LFXP2-8E-5FTN256C
Manufacturer:
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The general SED flow is as follows.
The user has two choices when an error is detected, ignore the error, and possibly log it, or reconfigure the FPGA.
Reconfiguration can be accomplished by driving the PROGRAMN pin low. This can be done by externally connect-
ing a GPIO pin to PROGRAMN.
Figure 16-4. Example Schematic
SED Run Time
The amount of time needed to perform an SED check depends on the density of the device and the frequency of
SEDCLKIN. There will also be some overhead time for calculation, but it is fairly short in comparison. An approxi-
mation of the time required can be found by using the following formula:
Maxbits is in mega-bits and depends on the density of the FPGA (see Table 16-8). SEDCLKIN is frequency in MHz.
Time is in seconds
For example, for a design using a LatticeXP2 with 5K look-up tables and the SEDCLKIN is the software default of
3.1 MHz:
In this example, SED checking will take approximately 398.71 ms. Remember that this happens in the background
and does not affect user logic performance.
Note that the internal oscillator used to generate SEDCLKIN can vary by ±30%.
1. User logic sets SEDENABLE high. This signal may be tied high if desired.
2. User logic sets SEDSTART high. SEDINPROG goes high. If SEDDONE is already high it is driven low.
3. SED starts reading back data from the configuration SRAM.
4. SED finishes checking. SEDERR is updated, SEDINPROG goes low, and SEDDONE goes high.
5. If SEDERR is driven high there are only two ways to reset it, drive SEDENABLE low or reconfigure the
6. SEDENABLE goes low when/if the user specifies, and SED is no longer in use.
SEDSTART may be tied high to enable continuous SED checking.
FPGA.
Maxbits / SEDCLKIN = Time
1.236 Mbits / 3.1 MHz = 398.71 ms
LatticeXP2
PROGRAMN
GPIO
16-5
VCC
Open Drain
Output
10K
Detection Usage Guide
LatticeXP2 Soft Error
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