PCF2127AT/1,518 NXP Semiconductors, PCF2127AT/1,518 Datasheet - Page 58

• Manufacturer Part Number: PCF2127AT/1,518
• Description: IC RTC/CALENDAR TCXO QTZ 20SOIC
• Manufacturer: NXP Semiconductors
• Type: Clock/Calendar/Alarmr

Specifications of PCF2127AT/1,518

• Package / Case: 20-SOIC (0.300", 7.50mm Width)
• Time Format: HH:MM:SS (12/24 hr)
• Memory Size: 512B
• Date Format: YY-MM-DD-dd
• Interface: I²C, 2-Wire Serial
• Voltage - Supply: 1.8 V ~ 4.2 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Function: Serial Clock, Timestamp, Timekeeper, Watchdog, Alarm, Calendar, Timer, Timer Interrupt
• Rtc Memory Size: 512 bytes
• Supply Voltage (max): 4.2 V
• Supply Voltage (min): 1.8 V
• Mounting Style: SMD/SMT
• Rtc Bus Interface: I2C
• Supply Current: 2600 nA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
PCF2127A_2
Product data sheet
Fig 40. System configuration
SCL
SDA
9.2.4 Acknowledge
9.2.5 I
TRANSMITTER
RECEIVER
MASTER
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
Acknowledgement on the I
After a start condition a valid hardware address has to be sent to a PCF2127A device.
The appropriate I
is shown in
2
Fig 41. Acknowledgement on the I
•
•
•
•
C-bus protocol
A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
by transmitter
data output
by receiver
data output
SCL from
master
Table
RECEIVER
SLAVE
All information provided in this document is subject to legal disclaimers.
2
59.
C-bus slave address is 1010001. The entire I
condition
START
S
Rev. 02 — 7 May 2010
2
C-bus is illustrated in
TRANSMITTER
RECEIVER
SLAVE
1
2
C-bus
Integrated RTC, TCXO and quartz crystal
2
TRANSMITTER
Figure
MASTER
41.
not acknowledge
acknowledge
2
8
C-bus slave address byte
TRANSMITTER
PCF2127A
RECEIVER
MASTER
acknowledgement
clock pulse for
© NXP B.V. 2010. All rights reserved.
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