OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 186

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
11.7.5.1 Selecting the appropriate I
11.7.5 I
Table 185. I
I2SCLL- 0x4000 0014)
Table 186. I
Table 187. I
Software must set values for the registers I2SCLH and I2SCLL to select the appropriate
data rate and duty cycle. I2SCLH defines the number of I2C_PCLK cycles for the SCL
HIGH time, I2SCLL defines the number of I2C_PCLK cycles for the SCL low time. The
frequency is determined by the following formula (I2C_PCLK is the frequency of the
peripheral bus APB):
The values for I2SCLL and I2SCLH must ensure that the data rate is in the appropriate
I
gives some examples of I
I2SCLH values.
Table 188. I2SCLL + I2SCLH values for selected I2C_PCLK values
Bit Symbol
0
7:1 Address
31:
8
Bit
15:0
31:16
Bit
15:0
31:16
I
100 kHz (Standard)
400 kHz (Fast Mode)
1 MHz (Fast Mode Plus)
2
2
2
C data rate range. Each register value must be greater than or equal to 4.
C SCL HIGH and LOW duty cycle registers (SCLH - 0x4000 0010 and
C mode
GC
-
Symbol
SCLH
-
Symbol
SCLL
-
2
2
2
C Slave Address register 0 (ADR0- 0x4000 000C) bit description
C SCL HIGH Duty Cycle register (SCLH - address 0x4000 0010) bit description
C SCL Low duty cycle register (SCLL - 0x4000 0014) bit description
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Description
General Call enable bit.
The I
Reserved
Description
Count for SCL HIGH time period selection.
Reserved
Description
Count for SCL low time period selection.
Reserved
2
C device address for slave mode.
Rev. 1.1 — 10 March 2011
I 2 C
2
6
60
15
-
C-bus rates based on I2C_PCLK frequency and I2SCLL and
bitfrequency
2
C data rate and duty cycle
8
80
20
8
=
-------------------------------------------------------- -
I2CSCLH
10
100
25
10
Chapter 11: LPC122x I2C-bus controller
I2CPCLK
I2C_PCLK (MHz)
SCLH + SCLL
+
120
12
30
12
I2CSCLL
16
160
40
16
UM10441
© NXP B.V. 2011. All rights reserved.
20
200
50
20
0x00
Reset value
0x0004
-
Reset value
0x0004
-
Reset value
0
-
Table 188
30
300
75
30
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