OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 22

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
4.5.14 System AHB clock control register
Table 20.
The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.
The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock
for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the SYSCON block, and
the PMU. This clock cannot be disabled.
Table 21.
5
6
Bit
7:0
31:8
Bit
0
1
2
3
4
Symbol
DIV
-
Symbol
SYS
ROM
RAM
FLASHREG
FLASHARRAY
I2C
CRC
System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit
description
System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
All information provided in this document is subject to legal disclaimers.
Description
System AHB clock divider values
0: System clock disabled.
1: Divide by 1.
to
255: Divide by 255.
Reserved
Rev. 1.1 — 10 March 2011
Value
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Description
Enables clock for AHB to APB bridge, to the AHB
matrix, to the Cortex-M0 FCLK and HCLK, to the
SysCon, and to the PMU. This bit is read only.
Reserved
Enable
Enables clock for ROM.
Disable
Enable
Enables clock for RAM.
Disable
Enable
Enables clock for flash controller registers.
Disable
Enable
Enables clock for flash array.
Disable
Enable
Enables clock for I2C.
Disable
Enable
Enables clock for CRC.
Disable
Enable
Chapter 4: LPC122x System control (SYSCON)
UM10441
© NXP B.V. 2011. All rights reserved.
22 of 442
Reset
value
1
1
1
1
1
1
1
Reset
value
1
0x00