OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 49

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
4.7.3.3 Wake-up from Deep-sleep mode
4.7.4.1 Power configuration in Deep power-down mode
4.7.4.2 Programming Deep power-down mode
4.7.4 Deep power-down mode
The microcontroller can wake up from Deep-sleep mode in the following ways:
Remark: If the watchdog oscillator is running in Deep-sleep mode, its frequency
determines the wake-up time causing the wake-up time to be longer than waking up with
the 12 MHz IRC.
In Deep power-down mode, power and clocks are shut off to the entire microcontroller
with the exception of the WAKEUP pin. The microcontroller is blocked from entering Deep
power-down mode when the WDLOCKDP bit is set to one in the WDMODE register
(Table
If the RTC is enabled before entering Deep power-down mode, the RTC and the RTC
oscillator continue to run in Deep power-down mode. If the RTC is not needed in Deep
power-down mode, disable the RTC to minimize power consumption.
During Deep power-down mode, the contents of the SRAM and registers are not retained
except for a small amount of data which can be stored in four 32-bit general purpose
registers of the PMU block.
All functional pins are tri-stated in Deep power-down mode except for the WAKEUP pin.
Deep power-down mode has no configuration options. All clocks, the core, and all
peripherals except for the RTC and the RTC oscillator are powered down. Only the
WAKEUP pin and the backup registers are powered. The low-power RTC and the RTC
oscillator can be left running (this is the default).
Remark: The microcontroller can only enter Deep-power down mode if the WDLOCKDP
bit is set to 0 in the WDMODE register
must be reset before the Deep power-down mode can be entered.
The following steps must be performed to enter Deep power-down mode:
1. Write one to the DPDEN bit in the PCON register (see
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Signal on an external pin. For this purpose, pins PIO0_0 to PIO0_11 can be enabled
as inputs to the start logic. The start logic does not require any clocks and generates
the interrupt if enabled in the NVIC to wake up from Deep-sleep mode.
RTC match interrupt for self-timed wake-up. The RTC interrupt must be enabled in the
start logic1 block.
Reset from the BOD circuit. In this case, the BOD circuit must be enabled in the
PDSLEEPCFG register, and the BOD reset must be enabled in the BODCTRL
register
Reset from the watchdog timer. In this case, the watchdog oscillator must be running
in Deep-sleep mode (see PDSLEEPCFG register), and the WDT must be enabled in
the SYSAHBCLKCTRL register.
External RESET pin.
264).
(Table
All information provided in this document is subject to legal disclaimers.
32).
Rev. 1.1 — 10 March 2011
(Table
Chapter 4: LPC122x System control (SYSCON)
264). If WDLOCKDP = 1, the microcontroller
Table
56).
UM10441
© NXP B.V. 2011. All rights reserved.
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