OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 338

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
21.7 Functional description
Table 341. DMA control signals
UM10441
User manual
Signal
DMA channel
request
DMA single
channel request
DMA channel
request control
DMA stall
21.6.20 Channel DMA interrupt enable register
21.7.1 DMA control signals
Name
dma_req[c]
dma_sreq[c]
dma_waitonreq[c] Peripheral/
dma_stall[c]
This register is a read/write register and enables the completion of a DMA transfer to
create an interrupt for DMA channel c (c = 0 to 20). Writing to a bit where a DMA channel
is not implemented has no effect.
Table 340. Channel DMA interrupt enable register (CHNL_IRQ_ENABLE, address 0x4004
The DMA control signals for DMA transfers and for providing the handshake for
peripheral-to-memory transfers are listed in
Bit
20:0
31:21
Symbol
CHNL_IRQ_
ENABLE
-
C088) bit description
Source/
destination
Peripheral/
controller
Peripheral/
controller
controller
Peripheral/
controller
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
Description
The peripheral asserts dma_req[c] when it has one or more data
transfers that require servicing. The controller services the request by
performing the DMA cycle using 2
arbitration between transfers depending on the setting of R_power (see
Table
channel c is complete. Then the request is deasserted. All peripherals
wait for a transfer request to clear before starting the next transfer.
The peripheral asserts dma_sreq when it has one data transfer that
requires servicing. The controller services the request by performing
the DMA cycle using one single DMA transfer. The dma_sreq[c] signal
stays HIGH until the transfer for channel c is complete. Then the
request is deasserted. All peripherals wait for a transfer request to clear
before starting the next transfer.
When a group of 2
controller from deasserting dma_active, until the corresponding
dma_req, or dma_sreq, is negated.
The peripheral can use dma_stall to extend the current DMA cycle.
Peripherals that are slow to deassert a request, after a DMA transfer
commences, might inadvertently trigger an additional request. Under
these circumstances, the peripheral must assert dma_stall until the
request can be negated.
345). The dma_req[c] signal stays HIGH until the transfer for
Description
Enables the DMA done (dma_done[c]) signal to
create an interrupt.
Write as:
Bit[c] = 0: DMA done interrupt disabled for channel c.
Bit[c] = 1: DMA done interrupt enabled for channel c.
Reserved.
R
DMA transfers complete, this signal prevents the
Table
341.
R
DMA transfers with possible
UM10441
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338 of 442
Reset
value
0x0
-