IS42S32800B-7BL INTEGRATED SILICON SOLUTION (ISSI), IS42S32800B-7BL Datasheet - Page 3

• Manufacturer Part Number: IS42S32800B-7BL
• Description: IC, SDRAM, 256MBIT, 143MHZ, BGA-90
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS42S32800B-7BL

• Memory Type: DRAM - Sychronous
• Access Time: 7ns
• Page Size: 256Mbit
• Ic Interface Type: Parallel
• Memory Case Style: BGA
• No. Of Pins: 90
• Operating Temperature Range: 0°C To +70°C
• Termination Type: SMD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 1.Pin Details of IS42S32800B
Symbol
CLK
CKE
BS0,BS1 Input
A0-A11 Input
CS#
RAS#
CAS#
WE#
DQM0-3 Input
DQ0-31 Input/Output
PIN DESCRIPTIONS
IS42S32800B
Integrated Silicon Solution, Inc.
Rev. F
07/21/09
Type
Input
Input
Input
Input
Input
Input
of CLK.CLK also increments the internal burst counter and controls the output registers.
chronously with clock(set-up and hold time same as other inputs),the internal clock is suspended
from the next clock cycle and the state of output and burst address is frozen as long as the CKE
remains low.When all banks are in the idle state,deactivating the clock controls the entry to the
Power Down and Self Refresh modes.CKE is synchronous except after the device enters Power
Down and Self Refresh modes,where CKE becomes asynchronous until exiting the same mode.
The input buffers,including CLK,are disabled during Power Down and Self Refresh modes,providing
low standby power.
command is being applied.
Read/Write command (column address A0-A8 with A10 defining Auto Precharge) to select one
location in the respective bank.During a Precharge command,A10 is sampled to determine if all
banks are to be precharged (A10 =HIGH).
The address inputs also provide the op-code during a Mode Register Set .
commands are masked when CS#is sampled HIGH.CS#provides for external bank selection on
systems with multiple banks.It is considered part of the command code.
CAS#and WE#signals and is latched at the positive edges of CLK.When RAS# and CS#are as-
serted “LOW”and CAS#is asserted “HIGH,”either the BankActivate command or the Precharge
command is selected by the WE#signal.When the WE#is asserted “HIGH,”the BankActivate com-
mand is selected and the bank designated by BS is turned on to the active state.When the WE#is
asserted “LOW,”the Precharge command is selected and the bank designated by BS is switched to
the idle state after the precharge operation.
RAS#and WE#signals and is latched at the positive edges of CLK. When RAS#is held “HIGH”and
CS#is asserted “LOW,”the column access is started by asserting CAS#”LOW.”Then,the Read or
Write command is selected by asserting WE# “LOW”or “HIGH.”
CAS#signals and is latched at the positive edges of CLK.The WE#input is used to select the
BankActivate or Precharge command and Read or Write command.
buffers are placed in a high-z state when DQM is sampled HIGH.Input data is masked when DQM
is sampled HIGH during a write cycle.Output data is masked (two-clock latency)when DQM is
sampled HIGH during a read cycle.DQM3 masks DQ31-DQ24,DQM2 masks DQ23-DQ16,DQM1
masks DQ15-DQ8,and DQM0 masks DQ7-DQ0.
CLK.The I/Os are byte-maskable during Reads and Writes.
Description
Clock:CLK is driven by the system clock.All SDRAM input signals are sampled on the positive edge
Clock Enable:CKE activates(HIGH)and deactivates(LOW)the CLK signal.If CKE goes low syn-
Bank Select:BS0 and BS1 defines to which bank the BankActivate,Read,Write,or BankPrecharge
Address Inputs:A0-A11 are sampled during the BankActivate command (row address A0-A11)and
Chip Select:CS#enables (sampled LOW)and disables (sampled HIGH)the command decoder.All
Row Address Strobe:The RAS#signal defines the operation commands in conjunction with the
Column Address Strobe:The CAS#signal defines the operation commands in conjunction with the
Write Enable:The WE#signal defines the operation commands in conjunction with the RAS#and
Data Input/Output Mask:DQM0-DQM3 are byte specific,nonpersistent I/O buffer controls. The I/O
Data I/O:The DQ0-31 input and output data are synchronized with the positive edges of
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